DMA Request Handling in Virtual Memory via Temporary Block

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Solution Overview

Problem

In computer systems with virtual memory environments, DMA transfers can cause data coherency issues due to asynchronous operations, leading to potential system crashes when data is moved from one memory block to another, as DMA controllers may write to the source block before the data is fully transferred, resulting in stale data at the destination block.

Innovation Solution

A virtual memory manager redirects DMA transfers to a temporary block, uses a Modification Recording Register (MRR) to track changes, and ensures data integrity by writing data from the temporary block to the destination block only after the transfer is complete and verifies no further DMA writes have occurred.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If DMA transfers are allowed to occur asynchronously in a virtual memory environment, then data transfer efficiency is improved, but data coherency problems occur causing system crashes

Engineering Contradiction:
Improvedata transfer efficiencyVSAvoiddata coherency
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

A temporary memory block is introduced as an intermediary between the source and destination blocks. The DMA controller writes to this temporary block instead of the final destination, and the virtual memory manager subsequently copies the data from the temporary block to the destination block. This intermediary mechanism allows asynchronous DMA operations while maintaining data coherency.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The system performs preliminary actions by first redirecting DMA writes to a temporary block before the actual data transfer is complete. The virtual memory manager proactively manages the temporary block and ensures data is copied to the destination only when appropriate, preventing stale data issues before they occur.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If the virtual memory manager frequently checks for DMA transfers during data movement, then data coherency is maintained, but processing time increases

Engineering Contradiction:
Improvedata coherencyVSAvoidprocessing time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The DMA controller itself maintains the Modification Recording Register, automatically tracking which memory blocks have been modified by DMA transfers. This self-service mechanism eliminates the need for the virtual memory manager to continuously check for DMA activity, reducing processing time while maintaining coherency.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The Modification Recording Register provides feedback to the virtual memory manager about which blocks have been modified by DMA. This feedback mechanism allows the system to efficiently determine when data needs to be copied without continuous polling, reducing the time loss associated with frequent checks.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS7725620B2Handling DMA requests in a virtual memory environment
Publication Date: 2010.05.25 LENOVO GLOBAL TECHNOLOGIES SWITZERLAND INTERNATIONAL GMBH
  • US7725620B2 patent drawing
  • US7725620B2 patent drawing
  • US7725620B2 patent drawing

AI summary

An apparatus includes a virtual memory manager that moves data from a first block to second block in memory. When the virtual memory manager is ready to transfer data from the first block to the second block, a third, temporary block of memory is defined. The translation table in a DMA controller is changed to point DMA transfers that target the first block to instead target the temporary block. The virtual memory manager then transfers data from the first block to the second block. When the transfer is complete, a check is made to see if the DMA transferred data to the temporary block while the data from the first block was being written to the second block. If so, the data written to the temporary block is written to the second block. A hardware register is preferably used to efficiently detect changes to the temporary block.