Cache Latch Circuit Inverse Length Optimization for Data I/O Rate
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Solution Overview
Problem
Current semiconductor devices have limitations in achieving high data input/output rates, particularly in nonvolatile memory devices which require efficient data processing and storage while maintaining data integrity without power supply.
Innovation Solution
The semiconductor device incorporates a memory array with page buffers, cache latch circuits, a column selector, and sense amplifiers, where the cache latch circuits are connected through column selection lines and data lines with an inverse relationship in length, optimizing data output rates by reducing column selection line loading and enhancing data transmission efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If cache latch circuits are connected to column selector through long column selection lines, then more cache latch circuits can be accommodated, but data input/output rate decreases due to increased loading
Solution Approach 1:
The patent applies inversion by reversing the conventional connection approach: instead of connecting all cache latch circuits to the column selector through long column selection lines, it connects only selected cache latch circuits (corresponding to selected columns) to the column selector. This inverted connection strategy reduces the number of active column selection lines and their loading, thereby improving data input/output rate while still accommodating multiple cache latch circuits through selective activation.
2Quantity of substance
If column selection lines are made longer to connect more cache latch circuits, then circuit capacity increases, but signal transmission speed decreases
Solution Approach 1:
The patent segments the connection between cache latch circuits and the column selector by introducing intermediate selection mechanisms. Instead of direct long-distance connections, the system divides the connection path into segments: column address → column decoder → selected cache latch circuits. This segmentation allows multiple cache latch circuits to be accommodated while keeping individual signal transmission paths short and fast.
3Productivity
If data lines are made shorter to improve transmission speed, then data output rate increases, but the number of sense amplifiers must increase
Solution Approach 1:
The patent applies universality by making sense amplifiers serve multiple functions and multiple data lines. Each sense amplifier is designed to handle data from multiple cache latch circuits through shared data lines, rather than dedicating one sense amplifier per data line. This multi-functional approach allows data lines to be kept short for high-speed transmission while reducing the total number of sense amplifiers required.
Data Source
AI summary
A semiconductor device includes a memory array including memory cells, page buffers suitable for reading data from the memory cells, cache latch circuits suitable for latching read data from the page buffers, and transmitting latched data to data lines in response to a column selection signal, a column selector suitable for outputting the column selection signal to the cache latch circuits through column selection lines in response to a column address, and sense amplifiers suitable for outputting transmitted data of the data lines by sensing voltages of the data lines, in which the cache latch circuits are connected to the column selector and the sense amplifiers through the column selection lines and the data lines, respectively, and have inverse relationship between the column selection lines and the data lines in length.