Read-Only Memories TRIZ Cases

A flash memory erase method using flags to identify and repair bit line leakage with slow program pulses.

A variable resistance memory device uses a command flag to activate a write driver for supplying program current to memory cells.

A switching memory cell connects or isolates stacked channel layers in a semiconductor device.

Applying boosting prevention voltage and equalizing voltage minimizes threshold voltage distribution shift caused by negative and positive boosting phenomena.

Programming distinct source select transistor states enables selective activation of parallel memory string groups during read operations.

An ECC engine translates read addresses and verifies error correcting codes to ensure safe execution in place from flash memory.

Applying negative substrate voltage suppresses band-to-band tunneling in unselected cells, reducing oxide damage.

An interpoly charge trapping structure segments the dielectric layer to resolve erase difficulties in planar memory cells by concentrating charge removal.

A stacked NAND flash memory cell executes a two-step voltage sequence that suppresses electron migration, preventing data retention degradation.

Control circuit boosts voltages to induce gate induced drain leakage current for efficient erase operations.

A real-time clock module controls power supply to an external memory device via a master interface circuit.

Inverse column selection and data line lengths reduce loading on cache latch circuits, resolving the contradiction between circuit capacity and signal speed.

A non-volatile memory erasing method uses targeted hole injection to adjust threshold voltages.

Hierarchical decoding with discharge devices manages signal lines to maintain consistent lengths across vertically stacked memory blocks.

An M:N tier mapping scheme minimizes peripheral circuitry area in non-volatile memory by coupling fewer sense amplifiers to multiple data latch tiers.

A DRAM chip uses a sustaining voltage generator coupled to storage capacitors during transistor turn-off periods.

A shaping code system encodes digit patterns to skew programmed data states toward lower threshold voltage levels.

A non-volatile memory system applies offset values to read currents from multiple cells before combining them to determine program states.

A non-volatile memory device isolates unit cell read current using latched sense amplifier enable signals and column switching control.

A cache page copy scheme uses adaptive full-sequence programming to relocate data across memory cells with minimal latch overhead.

Periodic maintenance pulses eliminate voids in phase change material to prevent heater degradation and extend operational lifespan.

Reference transistor elements replace bulky resistor arrays to reduce integrated circuit area while maintaining precise programming current control.

A wordline driver uses p-channel transistors to limit maximum voltage differentials across local drivers.

A control circuit generates verify result data in parallel for memory cell transistor groups to accelerate semiconductor memory write operations.

A memory system stores fewer bits per cell than its capacity to enable error validation through redundant data generation.

A semiconductor input buffer uses cross-coupled transistors and resistor networks to stabilize signal transitions.

Dynamic read level voltage adjustment compensates for wear induced threshold shifts across program erase cycles, reducing bit error rates.

A folded word line architecture reorganizes memory array geometry to reduce resistive and capacitive loading on signal paths.

A non-volatile storage device refreshes data based on programming timing to maintain integrity.

Segmented programming operations adjust selection device threshold voltages to mitigate parasitic interference and improve manufacturing yield.

Segmented power lines and signal fixing logic reduce current leakage during CPU reset while maintaining data retention.

A tunnel diode senses stored charges via quantum tunneling, preventing charge loss during read operations and extending retention time.

A tapered semiconductor body widens at the lower end of an intermediate insulating layer to prevent breakage caused by excessive thinning at step differences.

A two-pass programming technique coarsely programs memory cells to wide threshold regions before fine tuning them to precise levels.

Dynamic voltage adjustment during non-volatile memory cell programming stages resolves reliability and precision trade-offs.

Anti-phase bit line pre-charging reduces coupling capacitance, shortening pre-charge time and read operation duration.

A bias generator uses a replica circuit and charge pump to produce stable wordline and bitline voltages, compensating for temperature and process variations.

Control circuitry dynamically skips final verify steps based on loop thresholds, resolving the trade-off between programming speed and reliability.

A multi-level test sensing voltage method determines optimal read thresholds by analyzing cell count differentials across sequential voltage steps.

A tracking system records non-volatile repair categories in integrated circuits to enable efficient screening of unreliable parts.

A nonvolatile memory controller updates program start voltage storage units based on programming states to maintain optimal threshold distributions.

A reference cell circuit uses current mirrors to generate adjusted reference currents for non-volatile memory state determination.

Controller identifies bad blocks during manufacturing initialization using write-verify sequences, reducing MLC flash memory setup time.

Segmenting the gate into control and select parts resolves read speed versus data retention trade-offs in nonvolatile memory.

An N-way wave pipeline architecture segments clock signals to allow parallel data processing across multiple independent stages.

Address re-mapping replaces defective sub-blocks with non-defective ones within the same group, maintaining electrical characteristics while reducing chip size.

Segmented gate electrodes separate adjacent drain select plugs to improve write and read speeds while maintaining data integrity in vertical channel structures.

A nonvolatile memory device switches verify voltages to adapt writing conditions across packaging stages.

Embedded repair logic maps defective addresses to redundant memory, enabling field repairs without disassembly or proprietary analysis engines.

Adjustable column address scramble using fuses resolves simultaneous failures in multiple column planes by reconfiguring addresses to prevent collisions.