Column Address Scramble Using Fuses for Memory Repair
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Solution Overview
Problem
In memory systems, global column repair techniques fail to address simultaneous failures in multiple column planes, leading to address collisions and increased yield loss due to duplicate column address failures, which can render memory devices unrepairable and decrease operational efficiency.
Innovation Solution
Implementing an adjustable column address scramble using fuses in the column decoder to scramble column addresses experiencing errors, allowing the memory device to avoid collisions and enable repair of multiple column planes by reconfiguring addresses within the same column plane.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of repair
If global column repair techniques are used, then single column failures can be repaired, but simultaneous failures in multiple column planes cannot be addressed, leading to address collisions and increased yield loss
Solution Approach 1:
The invention divides the column address space into multiple segments by implementing separate repair mechanisms for each column plane. Each column plane can be independently repaired using plane-specific repair techniques, allowing simultaneous repair of multiple column planes without address collisions. This segmentation enables the memory device to handle multiple failures that would otherwise be unrepairable with global repair alone.
Solution Approach 2:
The invention adds a new dimension to the repair architecture by introducing plane-specific repair capabilities alongside global column repair. This multi-dimensional approach allows the system to repair failures in different column planes independently, transforming a single-dimensional global repair system into a multi-dimensional repair system that can simultaneously address failures across multiple planes without interference.
2Device complexity
If global column repair is implemented, then repair resources are consolidated, but duplicate column address failures in multiple planes cause address collisions that render devices unrepairable
Solution Approach 1:
The repair architecture is segmented into global column repair components and plane-specific repair components. Each segment handles specific repair tasks: global repair addresses common column failures, while plane-specific repair handles failures unique to individual column planes. This segmentation eliminates address collisions by providing dedicated repair paths for each plane, thereby reducing yield loss without significantly increasing overall system complexity.
Solution Approach 2:
The invention introduces intermediary repair mechanisms that act as mediators between the global column repair system and the column planes. These intermediaries (plane-specific repair circuits) translate and coordinate repair operations, ensuring that repairs in one plane do not conflict with repairs in other planes. This intermediary layer resolves address collisions while maintaining a relatively simple overall architecture.
3Device complexity
If no address scrambling is implemented, then the address decoder operates simply, but simultaneous column failures cause address collisions that prevent repair
Solution Approach 1:
The address scrambling function is implemented preliminarily in the address decoder, transforming column addresses before they are used for repair operations. This preliminary scrambling ensures that addresses from different column planes are differentiated, preventing collisions before they can occur during repair. By performing this action in advance, the system maintains a simple decoder architecture while ensuring reliable repair operations.
Data Source
AI summary
Methods, systems, and devices for adjustable column address scramble using fuses are described. A testing device may detect a first error in a first column plane of a memory array and a second error in a second column plane of the memory array. The testing device may identify a first column address of the first column plane associated with the first error and a second column address of the second column plane based on detecting the first error and the second error. The testing device may determine, for the first column plane, a configuration for scrambling column addresses of the first column plane to different column addresses of the first column plane. In some cases, the testing device may perform a fuse blow of a fuse associated with the first column plane to implement the determined configuration.