Parallel Bit Scan Control Circuit for Semiconductor Memory Write Speed
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Solution Overview
Problem
Current semiconductor memory devices face inefficiencies in completing the bit scan operation in a timely manner due to sequential processing of verify result data for each memory cell transistor, which prolongs the overall write operation.
Innovation Solution
Implementing a parallel processing method within the control circuit to generate verify result data for groups of memory cell transistors with different target threshold voltage states and subsequently calculating the number of transistors not reaching their target states in each group, thereby accelerating the bit scan operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If sequential processing method is used for verify result data, then processing accuracy is maintained, but bit scan operation time is excessively long
Solution Approach 1:
The patent divides verify result data into multiple groups corresponding to different target threshold voltage states (e.g., first group for first target state, second group for second target state). Each group is processed independently and in parallel by separate processing circuits, transforming a single sequential processing stream into multiple parallel streams. This segmentation enables simultaneous processing of different data groups without interfering with each other, significantly reducing total processing time while maintaining accuracy through dedicated processing paths for each group.
Solution Approach 2:
The patent combines multiple processing operations into a unified parallel processing framework where multiple processing circuits operate simultaneously on different groups of verify result data. The bit scan operation merges the results from all parallel processing circuits to determine the total number of transistors not reaching their target states. This merging approach allows the system to achieve the computational equivalence of sequential processing while benefiting from parallel execution speedup.
2Productivity
If parallel processing is implemented, then bit scan operation speed is improved, but control circuit complexity increases
Solution Approach 1:
The patent designs processing circuits that can handle multiple target threshold voltage states using a unified architectural framework. Each processing circuit is configured to process verify result data for a specific target state, but the overall system uses identical circuit designs replicated for different states, providing multi-functionality through replication rather than requiring fundamentally different circuit designs for each state. This universal approach balances parallel processing capability with circuit design simplicity.
Solution Approach 2:
The patent transitions from single-dimensional sequential processing to multi-dimensional parallel processing by introducing the dimension of concurrent operation across multiple target threshold voltage states. Instead of processing data groups one after another in time sequence, the system processes multiple groups simultaneously across different processing circuits, effectively adding a parallel execution dimension to the processing architecture. This dimensional change achieves speedup without requiring complex inter-circuit communication protocols.
Data Source
AI summary
A semiconductor memory device includes memory cell transistors and a control circuit. In a write operation, the control circuit executes multiple loops each including a program operation, a verify operation, and a bit scan operation. In the bit scan operation, the control circuit performs, a first process of generating verify result data in parallel for a group of memory cell transistors having different target threshold voltage states, the verify result data for each memory cell transistor in the group indicating whether the memory cell transistor has reached its target threshold voltage state, and a second process of calculating for each of the target threshold voltage states, the number of memory cell transistors that have not reached their target threshold voltage states.