Power Supply Circuit for Volatile Memory Data Retention
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Solution Overview
Problem
Existing electronic devices face challenges in efficiently managing power supply to volatile memory during transitions between operational states, leading to unnecessary current leakage and inefficient data retention.
Innovation Solution
An electronic device configuration that includes a non-volatile memory, a volatile memory, a controller part with a power supply part and signal fixing logic gates, and a power supply controller, which separates power supply lines to reduce current leakage by fixing output logic and maintaining self-refresh states in DRAM, even when the CPU is reset or powered off.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If power is supplied to volatile memory during CPU reset or power-off, then data retention is maintained, but current leakage increases
Solution Approach 1:
The power supply circuit is segmented into multiple independent power supply lines: a first power supply line for the CPU and a second power supply line for the volatile memory. This segmentation allows the volatile memory to maintain power supply independently during CPU reset or power-off events, ensuring data retention without requiring continuous power to the entire system. The separation of power supply paths enables selective power maintenance to reduce unnecessary current leakage from other components.
Solution Approach 2:
The power supply controller dynamically adjusts power supply based on operational states. During normal operation, both CPU and volatile memory receive power. During CPU reset or power-off, the controller maintains power supply to the volatile memory through the second power supply line while cutting power to the CPU through the first power supply line. This dynamic power management ensures data retention in volatile memory during transitions while minimizing overall power consumption and current leakage.
2Loss of energy
If power supply lines are separated, then current leakage is reduced, but device complexity increases
Solution Approach 1:
The power supply circuit is divided into distinct segments: a first power supply line connected to the CPU and a second power supply line connected to the volatile memory. Each segment can be independently controlled by the power supply controller, enabling selective power delivery. This segmentation, while increasing structural complexity, achieves the primary goal of reducing current leakage by allowing independent power management of different components based on their operational requirements.
3Reliability
If signal output logic is not fixed, then signal flexibility is maintained, but data retention is compromised during power transitions
Solution Approach 1:
The signal fixing circuit is configured in advance to automatically fix the output logic of signals from the volatile memory before power transitions occur. This preliminary configuration ensures that signal output logic is predetermined and stable during power-on, reset, or power-off events. The signal fixing circuit prepares the logic state beforehand, preventing data loss or signal instability during transitions while maintaining the flexibility of the system during normal operation.
Data Source
AI summary
An electronic device according to the present technique includes a non-volatile memory in which a program is stored, a volatile memory in which the program read from the non-volatile memory is stored, a controller part for controlling operations of the non-volatile memory and the volatile memory, and a power supply controller for controlling power to the controller part and the volatile memory. The controller part includes a power supply part and a signal fixing part. The power supply part is separated from another power supply line, and power for an interface signal of the volatile memory is supplied from the power supply part thereto. A voltage is supplied from the power supply part to the signal fixing part, and the signal fixing part fixes an output logic of the signal supplied to the volatile memory according to the signal from the power supply controller.