Non-Volatile Memory Multi-Bit Storage via Offset Current Combination
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Solution Overview
Problem
Conventional non-volatile memory devices can only store one bit of data per cell, limiting their capacity to store multiple discrete programming states due to close read current values for different states, making reliable programming and reading challenging.
Innovation Solution
The method involves reading currents from multiple memory cells, applying offset values to separate their read currents or voltages, and combining them to determine program states, allowing for the storage of multiple bits by spreading states across cells, ensuring non-overlapping current/voltage characteristics for unique identification.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple discrete programming states are stored in a single memory cell, then the memory capacity is increased, but the read current values for different states become too close together for reliable detection
Solution Approach 1:
The patent divides the storage of multiple bits into multiple separate memory cells instead of attempting to store all states in a single cell. Each cell stores a portion of the multi-bit data, and the combined read currents from multiple cells are used to determine the complete program state. This segmentation allows each individual cell to maintain distinct read current characteristics while the system as a whole achieves high storage capacity.
2Quantity of substance
If read currents from multiple memory cells are combined without offset adjustment, then the memory capacity increases, but the program states become unreliable due to overlapping current characteristics
Solution Approach 1:
The patent applies offset values to the read currents or voltages from different memory cells before combining them. These offsets shift the current characteristics of individual cells relative to each other, ensuring that the combined read currents for different program states do not overlap. This parameter adjustment maintains reliable state identification while enabling multi-bit storage across multiple cells.
3Productivity
If conventional single-bit memory cells are used, then the device complexity is low, but the productivity and storage capacity are limited
Solution Approach 1:
The patent combines multiple memory cells into a unified multi-bit storage system where the cells work together to store and retrieve multi-bit data. By merging the functionality of multiple cells and applying offset adjustments to their read currents, the system achieves high storage capacity and productivity while maintaining manageable complexity through systematic current combination and state determination.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables reliable storage and reading of multiple bits by increasing the separation between program states, enhancing the memory device's capacity and reliability by using multiple cells with offset adjustments.
Implementation Method 1
The high voltage drop between the floating gate 20 and control gate 22 will cause electrons on the floating gate 20 to tunnel from the floating gate 20, through the intervening insulation, to the control gate 22 by the well-known Fowler-Nordheim tunneling mechanism
Implementation Method 2
Electrons will then flow from the drain region 16 toward the source region 14, with some electrons becoming accelerated and heated whereby they are injected onto the floating gate 20
Data Source
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AI summary
A method of reading a memory device having a plurality of memory cells by, and a device configured for, reading a first memory cell of the plurality of memory cells to generate a first read current, reading a second memory cell of the plurality of memory cells to generate a second read current, applying a first offset value to the second read current, and then combining the first and second read currents to form a third read current, and then determining a program state using the third read current. Alternately, a first voltage is generated from the first read current, a second voltage is generated from the second read current, whereby the offset value is applied to the second voltage, wherein the first and second voltages are combined to form a third voltage, and then the program state is determined using the third voltage.