COP Memory Device Address Re-mapping for Defect Management
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Solution Overview
Problem
As information communication devices become more functional, there is a demand for nonvolatile memory devices with high integration and excellent electrical characteristics, but the complexity of operation circuits and wirings in three-dimensional memory devices can degrade memory cell electrical characteristics, necessitating a solution for grouping and addressing memory sub-blocks effectively.
Innovation Solution
A nonvolatile memory device with a control circuit that groups memory sub-blocks based on their physical and electrical characteristics, performs address re-mapping by replacing defective sub-blocks with non-defective ones within the same group, and controls address decoders and page buffer circuitry to maintain performance while reducing chip size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cell sizes are decreased to achieve high integration, then integration is improved, but the complexity of operation circuits and wirings degrades memory cell electrical characteristics
Solution Approach 1:
The memory device is divided into multiple memory sub-blocks organized in a three-dimensional structure with first and second vertical structures containing respective memory sub-blocks. This segmentation allows independent management and replacement of defective sub-blocks, maintaining electrical characteristics while achieving high integration through vertical stacking rather than horizontal expansion
Solution Approach 2:
The patent transitions from planar memory organization to three-dimensional vertical stacking, with memory sub-blocks arranged in vertical structures extending through multiple substrates. This dimensional change enables high integration density without increasing the footprint area, thereby avoiding the wiring complexity issues associated with scaled-down planar cells
2Reliability
If address re-mapping is implemented to replace defective memory sub-blocks, then reliability is improved, but device complexity increases
Solution Approach 1:
The control circuit pre-establishes mapping relationships between memory sub-blocks during manufacturing or initialization, storing replacement address information in advance. When a defective sub-block is detected, the pre-configured mapping enables immediate redirection of access operations without complex real-time computation, reducing operational complexity while maintaining reliability
Solution Approach 2:
The patent creates redundant copies of address mapping information within the control circuit, storing multiple representations of the memory layout including replacement paths. This copying strategy allows the system to handle defects through simple address substitution rather than complex dynamic remapping, reducing computational complexity while ensuring reliable access to replacement sub-blocks
Data Source
AI summary
A nonvolatile memory device includes a first semiconductor layer, a second semiconductor layer and a control circuit. The memory cell array includes a first vertical structure on the first upper substrate and a second vertical structure on the second upper substrate, the first vertical structure includes first sub-blocks and the second vertical structure includes second sub-blocks. The second semiconductor layer includes a lower substrate that includes address decoders and page buffer circuits. The first vertical structure includes first via areas in which one or more through-hole vias are provided, through-hole vias pass through the first vertical structure. The first sub-blocks are arranged among the first via areas and the second sub-blocks are arranged among the second via areas. The control circuit groups the memory blocks into a plurality of groups based on whether the memory blocks is close to the first via areas and performs address re-mapping.