Multi-Level Memory Cell Data Reliability via Redundant Bit Storage
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Solution Overview
Problem
Multi-level memory cells face challenges in maintaining data reliability due to the increased complexity of storing multiple bits in a single cell, which can lead to reduced reliability compared to single-level cells.
Innovation Solution
The implementation of a system that generates redundant data and stores fewer bits in each memory cell than it is capable of storing, using techniques such as duplicating and inverting bits based on a grey coding configuration, to enhance data reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multi-level memory cells store multiple bits in a single cell to increase storage capacity, then storage capacity is improved, but data reliability deteriorates
Solution Approach 1:
The patent applies copying by generating redundant data as a copy of the original data and storing it alongside the original data in the same multi-level memory cell. This redundant copy enables error detection and correction mechanisms to validate and correct the original data, thereby maintaining high data reliability while utilizing the full storage capacity of the multi-level cell.
2Reliability
If redundant data is generated and stored in addition to original data to enhance reliability, then data reliability is improved, but storage capacity is reduced
Solution Approach 1:
The patent merges the original data and redundant data into the same physical storage space by storing multiple bits in a single multi-level memory cell. Instead of allocating separate cells for original and redundant data, the system combines them in the same cell, efficiently utilizing the storage capacity while maintaining data reliability through redundancy.
3Reliability
If fewer bits are stored in each memory cell than the cell is capable of storing to increase reliability, then data reliability is improved, but storage capacity is reduced
Solution Approach 1:
The patent applies dynamics by making the number of stored bits configurable rather than fixed. The system can dynamically adjust how many bits are stored in each multi-level memory cell based on the required reliability level. When high reliability is needed, fewer bits are stored per cell with additional redundancy; when maximum capacity is needed, more bits are stored per cell with less redundancy, allowing flexible optimization between reliability and storage capacity.
Data Source
AI summary
Methods, systems, and devices for enhanced data reliability in multi-level memory cells are described. For a write operation, a host device may identify a first set of data to be stored by a set of memory cells at a memory device. Based on a quantity of bits within the first set of data being less than a storage capacity of the set of memory cells, the host device may generate a second set of data and transmit a write command including the first and second sets of data to the memory device. For a read operation, the host device may receive a first set of data from the memory device in response to transmitting a read command. The memory device may extract a second set of data from the first set of data and validate a portion of the first set of data using the second set of data.