Input Buffer Design for DDR4-SDRAM Voltage Shift Tolerance
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Solution Overview
Problem
Existing input buffers for DDR4-SDRAM struggle to maintain high data rates and performance tolerance when the reference voltage shifts, leading to a deterioration in slew rate due to the use of resistor loads coupled to positive power supply nodes and field-effect transistors with low threshold voltage.
Innovation Solution
The implementation of an input buffer design that includes a combination of transistors with different threshold voltages and resistor networks to stabilize the input signal, allowing operation across a wide voltage range and improving data rate performance through the use of cross-coupled and diode-connected transistors, along with bias transistors to manage voltage transitions effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If resistor loads are coupled to positive power supply nodes and field-effect transistors with low threshold voltage are used, then the data rate can be increased to 4.5 Gbps, but the slew rate deteriorates when the reference voltage shifts to a higher voltage
Solution Approach 1:
The patent changes the power supply voltage parameter for the resistor loads from the positive power supply voltage (VDD) to the mid-point reference voltage (VREF/2). This parameter change allows the input buffer to maintain proper operation and slew rate characteristics even when VREF shifts, while still achieving high data rates. The bias voltage for the transistors is also adjusted to maintain optimal operating points under varying reference voltage conditions.
2Reliability
If the reference voltage is shifted to a higher voltage, then the voltage margin for noise tolerance may be improved, but the time the input signal is greater than the reference voltage becomes shorter, causing the slew rate to deteriorate
Solution Approach 1:
The patent implements dynamic biasing where the bias voltage for the field-effect transistors is adjusted based on the reference voltage level. When VREF shifts to a higher voltage, the bias voltage is dynamically adjusted to maintain the appropriate overdrive voltage for the transistors, ensuring that the slew rate remains adequate while still operating with the shifted reference voltage that provides noise margin.
Data Source
AI summary
Apparatuses including a data input circuit of a semiconductor device are described. An example apparatus includes a first transistor that receives a reference voltage, a second transistor that receives an input signal, cross-couple type transistors, diode-connect type transistors and resistors. The cross-couple type resistors include a third transistor having a gate coupled to a drain of the second transistor, and a fourth transistor having a gate coupled to a drain of the first transistor. The diode-connect type transistors include a fifth transistor having a drain coupled to a drain of the third transistor, and a sixth transistor having a drain coupled to a drain of the fourth transistor. The resistors include a first resistor coupled between a gate and the drain of the fifth transistor and a second resistor coupled between a gate and the drain of the sixth transistor.