Semiconductor Memory Device Read Operation Boosting Prevention

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Solution Overview

Problem

Semiconductor memory devices experience read disturb due to negative and positive boosting phenomena during read operations, which affect the threshold voltage distribution of memory cells, leading to reduced reliability and data integrity.

Innovation Solution

A semiconductor memory device and method that apply a boosting prevention voltage to the cell string during an equalizing period after a read operation, minimizing negative and positive boosting, and maintaining channel voltage stability by applying an equalizing voltage to the word lines.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a read voltage is applied to a selected word line during a read operation, then data can be read from the selected memory cell, but negative and positive boosting phenomena occur in the channel region, causing read disturb and threshold voltage distribution shift

Engineering Contradiction:
Improvedata integrityVSAvoidread disturb
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent applies a boosting prevention voltage to the channel region before and during the read operation to counteract the negative and positive boosting phenomena. This preliminary anti-action prevents the threshold voltage distribution shift by establishing a counterbalancing electric field in the channel region, thereby reducing read disturb while maintaining data integrity

Inventive Principle:
Principle #9Preliminary anti-action

Solution Approach 2:

The patent changes the voltage parameter in the channel region by applying a specifically controlled boosting prevention voltage. This voltage parameter adjustment counteracts the boosting phenomena caused by the read operation, stabilizing the threshold voltage distribution and preventing read disturb without affecting the read operation functionality

Inventive Principle:
Principle #35Parameter changes

2Ease of operation

If read operations are performed on memory cells, then data access is enabled, but the threshold voltage distribution of memory cells shifts due to boosting phenomena, reducing reliability

Engineering Contradiction:
Improvedata accessVSAvoidthreshold voltage stability
Core Design Contradiction:
Ease of operationVSReliability

Solution Approach 1:

The boosting prevention voltage is applied in advance and concurrently with the read operation to prevent threshold voltage shifts before they occur. This preliminary counter-action maintains threshold voltage stability while allowing normal data access operations to proceed without interruption

Inventive Principle:
Principle #9Preliminary anti-action

Solution Approach 2:

The boosting prevention voltage acts as an intermediary element between the read voltage application and the memory cell channel region. It mediates the interaction by introducing a counterbalancing electric field that prevents the harmful boosting effects while allowing the read operation to function normally

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS11699487B2Semiconductor memory device performing read operation, and method for the semiconductor memory device
Publication Date: 2023.07.11 SK HYNIX INC
  • US11699487B2 patent drawing
  • US11699487B2 patent drawing
  • US11699487B2 patent drawing

AI summary

A semiconductor memory device includes a cell string and a peripheral circuit. The cell string includes at least one drain select transistor that is connected to a bit line, at least one source select transistor that is connected to a common source line, and a plurality of memory cells that are connected between the drain select transistor and the source select transistor. The peripheral circuit performs a read operation on a selected memory cell among the plurality of memory cells. The peripheral circuit is configured to read data that is stored in the selected memory cell by applying a read voltage to a selected word line among word lines that are connected to the plurality of memory cells and by applying a pass voltage to unselected word lines, and configured to transmit a boosting prevention voltage to a channel region in the cell string while applying an equalizing voltage to the word lines.