ECC Engine for Safe Execution in Place from Flash Memory

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Current flash devices do not cost-effectively provide the necessary protection mechanisms to meet the functional safety requirements for systems-on-a-chip (SOCs) used in advanced driver assistance systems, particularly in preventing soft errors and circuit failures that can occur due to radiation, noise, and aging.

Innovation Solution

Incorporating an error correcting code (ECC) engine between the processor and flash interface controller, which translates read/write addresses to ECC block addresses, verifies ECC codes, and corrects errors in flash memory access, ensuring safe execution in place (XIP) from flash memory.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If current flash devices are used for XIP processing, then cost and size constraints are met, but functional safety requirements cannot be satisfied due to lack of protection mechanisms

Engineering Contradiction:
Improvefunctional safetyVSAvoidprotection mechanisms
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

An ECC engine is introduced as an intermediary component between the processor and flash memory interface controller. This mediator performs error detection and correction operations on data being executed from flash memory, enabling functional safety without requiring the flash memory device itself to be complex or expensive. The ECC engine handles the protection mechanism functions separately, allowing the use of cost-effective flash devices while still meeting safety requirements.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If protection mechanisms are added to flash devices to meet safety requirements, then functional safety is improved, but cost effectiveness deteriorates

Engineering Contradiction:
Improvefunctional safetyVSAvoidcost effectiveness
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The system is segmented into separate functional components: the flash memory device handles only storage and basic data transfer, while the ECC engine handles error protection functions. This segmentation allows the use of inexpensive, simple flash devices for XIP processing while offloading the complex and costly protection mechanisms to a dedicated ECC engine, thereby maintaining cost effectiveness while achieving functional safety.

Inventive Principle:
Principle #1Segmentation

3Reliability

If soft error protection is implemented in flash memory, then reliability against radiation and noise is improved, but device complexity increases

Engineering Contradiction:
Improvesoft error protectionVSAvoiderror protection circuitry
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The ECC engine serves as an intermediary that provides soft error protection without requiring complex protection circuitry within the flash memory device itself. The ECC engine performs error detection and correction on data read from flash memory before it reaches the processor, thereby protecting against soft errors from radiation and noise while keeping the flash memory device simple and cost-effective.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS10388392B2Safe execution in place (XIP) from flash memory
Publication Date: 2019.08.20 TEXAS INSTRUMENTS INC
  • US10388392B2 patent drawing
  • US10388392B2 patent drawing
  • US10388392B2 patent drawing

AI summary

A device is provided that includes a processor, a flash memory configured to store error correcting code (ECC) blocks for execution in place (XIP) processing by the processor, wherein an ECC block includes a data block and an ECC code for the data block, a flash interface controller coupled to the flash memory, and an error correcting code (ECC) engine coupled between the processor and the flash interface controller, wherein the ECC engine is configured to receive a read command for the flash memory from the processor, to translate a read address to an ECC block address, to read the ECC block at the ECC block address from the flash memory via the flash interface controller, and to verify the ECC code in the read ECC block.