Reference Cell Circuit for Non-Volatile Memory Data Retention
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Solution Overview
Problem
As process technology advances, non-volatile memory devices face increasing difficulties in meeting high-quality data retention requirements due to the complexity of managing floating gate transistors in electrically erasable and programmable memory devices.
Innovation Solution
A reference cell circuit is introduced, comprising a reference cell array with floating gate transistors having an ultraviolet threshold voltage, a first current mirror circuit, and a second current mirror circuit, which generates and adjusts a reference current based on enable signals to determine the logical state of memory cells, optimizing data retention and reducing circuit layout area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional floating gate transistors are used in non-volatile memory, then data storage functionality is achieved, but data retention requirements become increasingly difficult to meet as process technology advances
Solution Approach 1:
The patent extracts and eliminates the program and erase circuits from the memory device by using ultraviolet threshold-based floating gate transistors that inherently maintain their threshold voltage without requiring active program/erase operations, thereby simplifying the overall device structure while maintaining data retention reliability
Solution Approach 2:
The patent changes the threshold voltage parameter of the floating gate transistors to an ultraviolet threshold level, which provides stable data retention characteristics without requiring complex program and erase circuitry, thus resolving the contradiction between reliability and device complexity
2Ease of operation
If program and erase circuits are included in the memory device, then floating gate transistor functionality is fully supported, but circuit layout area increases
Solution Approach 1:
The patent removes the program and erase circuits from the memory device by utilizing ultraviolet threshold-based floating gate transistors that maintain their functionality without requiring these additional circuits, thereby reducing the overall layout area while preserving essential transistor operations
Solution Approach 2:
The ultraviolet threshold-based floating gate transistors provide multi-functionality by inherently supporting data storage and retention without requiring separate program and erase circuitry, thus reducing layout area while maintaining full operational capability
3Measurement precision
If multiple floating gate transistors are used in the reference cell array, then reference current generation is improved, but the number of transistors and circuit complexity increase
Solution Approach 1:
The patent uses current mirror circuits to replicate and amplify the reference current generated by a minimal number of ultraviolet threshold-based floating gate transistors, thereby achieving accurate reference current levels without requiring a large number of transistors in the reference cell array
Solution Approach 2:
The patent changes the threshold voltage parameter to ultraviolet levels, which enables accurate reference current generation with fewer transistors due to the stable and predictable electrical characteristics of ultraviolet threshold-based devices
Data Source
AI summary
The present invention discloses a reference cell circuit which is applied to a non-volatile memory. The reference cell circuit includes a reference cell array, a first current mirror circuit, and a second current mirror circuit. The reference cell array includes at least one row of floating gate transistors. The first current mirror circuit is arranged to generate a mirror current according to a reference current generated by the reference cell array. The second current mirror circuit is arranged to receive the mirror current and generate an adjusted reference current according to the mirror current and a selected one of a plurality of enable signals, wherein the plurality of enable signals correspond to a plurality operations of the non-volatile memory and the adjusted reference current is arranged to determine logical state of a plurality of memory cells of the non-volatile memory.