Flash Memory Read Level Adjustment for Endurance
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Solution Overview
Problem
Multi-level cell (MLC) flash memory devices experience significant degradation in endurance due to increased program/erase cycles, leading to higher error rates and reduced reliability, making them unsuitable for enterprise applications despite their increased data capacity.
Innovation Solution
A method and system for dynamically adjusting read level voltages in flash memory cells by predicting and estimating new read levels based on factors such as die temperature, process corners, block location, and program/erase cycles, thereby reducing the number of read retries and improving memory cell endurance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multi-level cell (MLC) flash memory is used to increase data capacity, then storage capacity is improved, but program/erase cycle endurance deteriorates due to increased wear stresses
Solution Approach 1:
The patent implements dynamic read level adjustment that adapts to changing memory cell conditions based on P/E cycle count, temperature, and retention time. The read level voltage is continuously optimized rather than fixed, allowing the system to maintain reliable reads despite degradation from increased P/E cycles enabled by MLC architecture
Solution Approach 2:
The system changes the read level voltage parameter dynamically based on multiple factors including P/E cycle count, temperature, and retention time. By adjusting this critical parameter, the system compensates for wear-induced threshold voltage shifts and maintains accurate data retrieval across the full range of P/E cycles
2Device complexity
If read level voltage is fixed at beginning of life, then device complexity is reduced, but measurement precision deteriorates as memory degrades over time
Solution Approach 1:
The patent implements a feedback mechanism where read level accuracy is monitored through prediction indicators and comparison with prediction values. Based on this feedback, the system determines whether to update read levels dynamically, ensuring high measurement precision while avoiding unnecessary adjustments that would increase complexity
Solution Approach 2:
The system performs self-adjustment of read levels by automatically detecting degradation patterns and compensating for them. The memory controller monitors its own performance metrics and autonomously adjusts read parameters without external intervention, maintaining precision while minimizing added complexity
3Reliability
If dynamic read level adjustment is implemented, then reliability is improved through reduced bit error rates, but device complexity increases due to additional control mechanisms
Solution Approach 1:
The patent performs preliminary estimation of read level requirements based on predicted P/E cycle counts, temperature, and retention time before actual read operations. This advance preparation allows the system to pre-position read levels optimally, reducing the need for complex real-time adjustments during critical read operations
Data Source
AI summary
Disclosed is an apparatus and method for determining a read level voltage to apply to a block of memory cells in a non-volatile memory circuit. A prediction value is compared to a prediction indicator to determine whether a new read level voltage to be applied to read the memory cells should be estimated. If a new read level should be estimated the new read level is calculated as a function of an initial read level and a dwell time and a number of program/erase cycles. A controller provides one or more programming commands representative of the new read level voltage to the memory circuit to read the cells.