Memory Repair Logic for Defective Address Redundancy Mapping
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Solution Overview
Problem
Existing memory technologies lack the ability to effectively repair defective memory locations after the memory has been assembled by a customer, as they do not include an analysis engine for resolving redundancy solutions, leading to undesirable disassembly and replacement processes.
Innovation Solution
Incorporation of memory repair logic and fuse banks that allow for the mapping of defective memory addresses to redundant memory, enabling external memory testers to program programmable elements to redirect access from defective to redundant memory locations, even after manufacturing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of repair
If memory testing and repair is performed only by the manufacturer before memory is provided to customers, then the manufacturer can use proprietary analysis engines to resolve redundancy solutions, but customers cannot repair defective memory locations after assembly, requiring disassembly and replacement
Solution Approach 1:
The patent extracts the repair capability from the manufacturing environment and embeds it directly into the memory device. The analysis engine and redundancy resolution logic are integrated into the memory chip itself, allowing customers to perform repairs without needing proprietary manufacturing infrastructure. This enables field repair while eliminating the need for complex external analysis systems.
Solution Approach 2:
The memory device becomes self-repairing by incorporating the analysis engine and repair logic within the device itself. When defective locations are detected, the integrated system automatically resolves redundancy solutions and reconfigures the memory mapping without requiring external manufacturing equipment or proprietary software, enabling the device to service itself in the field.
2Ease of operation
If external memory testers are used to test memory after customer assembly, then testing can be performed in the field, but the testers lack the analysis engine to resolve redundancy solutions, making repair impossible
Solution Approach 1:
The patent merges the testing capability with the repair capability by integrating the analysis engine directly into the memory device. This combination allows external testers to simply identify defective locations while the integrated analysis engine automatically resolves redundancy solutions and performs the repair, unifying both functions in a single system.
Solution Approach 2:
The integrated analysis engine acts as an intermediary between the external tester and the memory array. The external tester identifies defective locations and communicates them to the analysis engine, which then resolves the redundancy solution and reconfigures the memory mapping, bridging the gap between simple testing and complex repair operations.
3Reliability
If defective memory locations are replaced or the entire assembly is discarded, then functional memory is restored, but damage and waste occur during disassembly and replacement
Solution Approach 1:
Instead of discarding or physically replacing defective memory locations, the patent recovers functionality by reconfiguring the memory mapping to use redundant locations. The defective physical locations are effectively discarded from active use, but the memory assembly itself is preserved and recovered for continued operation, eliminating the need for physical replacement.
Solution Approach 2:
The patent prepares redundant memory locations in advance during manufacturing, so when defective locations are detected later, the repair can be performed immediately by reconfiguring to the pre-prepared redundant locations. This preliminary preparation eliminates the need for physical replacement or disassembly, as the repair resources are already in place.
Data Source
AI summary
Memories, memory repair logic, and methods for repairing a memory having redundant memory are disclosed. One such memory includes programmable elements associated with respective redundant memory configured to have memory addresses mapped thereto, the programmable elements configured to be programmed with at least portions of the memory addresses. Such a memory further includes repair logic coupled to the programmable elements and configured to identify programmable elements available for programming to map memory addresses to respective redundant memory. One method for remapping a memory address of a memory to redundant memory includes receiving at least a portion of a memory address to be remapped to redundant memory, determining whether a programmable element associated with the redundant memory is available for programming, and when a programmable element is available, programming the programmable element such that the memory address will be mapped to the associated redundant memory.