Folded Word Line Architecture for Memory Array RC Delay Reduction
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Solution Overview
Problem
Shrinking memory arrays face challenges such as increased sheet resistance, current density, and capacitive loading, leading to high resistive-capacitive (RC) delay and unacceptable soft error rates due to limited design choices and spacings, which existing technologies struggle to address effectively.
Innovation Solution
Implementing a memory array with a folded architecture for word lines, allowing for reduced current density and improved electromigration, and enabling new configurations while maintaining required spacings to avoid excessive multi-bit upsets, by using concurrently active word lines and shared word line drivers to reduce resistive and capacitive loading.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If memory arrays are shrunk to reduce area, then area occupied by memory array is reduced, but sheet resistance increases and current density increases
Solution Approach 1:
The patent transitions from a conventional linear word line layout to a folded word line architecture that utilizes two-dimensional space more efficiently. By folding the word lines back on themselves, the design maintains adequate spacing between adjacent word lines while reducing the overall footprint of the memory array. This dimensional reorganization allows the memory array to meet area reduction targets without compromising the electrical performance and reliability of the word lines.
2Area of stationary object
If memory arrays are shrunk to reduce area, then area occupied by memory array is reduced, but capacitive loading on word lines increases
Solution Approach 1:
The folded word line architecture reorganizes the spatial arrangement of word lines to reduce their total length and minimize overlapping capacitance. By folding the word lines in a systematic pattern, the design reduces the capacitive loading on each word line while maintaining the increased memory cell density. This dimensional reorganization directly addresses the capacitive loading issue that arises from array shrinkage.
3Area of stationary object
If word lines are narrowed to reduce area, then area occupied by memory array is reduced, but RC delay increases
Solution Approach 1:
The folded word line layout optimizes the geometric arrangement to minimize the total length of word lines while maintaining adequate width. By organizing word lines in a folded pattern rather than a simple linear extension, the design reduces the RC delay associated with narrower word lines. The folded architecture achieves better electrical performance by reducing the effective signal path length without requiring increased word line width.
4Quantity of substance
If spacing between memory cells is reduced to increase density, then memory cell density increases, but multi-bit upsets increase leading to unacceptable soft error rate
Solution Approach 1:
The folded word line architecture provides an additional spatial dimension for organizing memory cells and maintaining separation distances. By utilizing the folded layout, the design can maintain the required spacing between memory cells to prevent multi-bit upsets while achieving higher overall density through more efficient space utilization. The folded structure creates natural separation zones that help maintain acceptable soft error rates despite increased density.
Data Source
AI summary
According to an exemplary embodiment, a memory array arrangement includes a plurality of word lines, where at least two of the plurality of word lines are concurrently active word lines. Each of the plurality of word lines drive at least one group of columns. The memory array arrangement also includes a multiplexer for coupling one memory cell in a selected group of columns to at least one of the plurality of sense amps, thereby achieving a reduced sense amp-to-column ratio. The memory array arrangement further includes a plurality of I/O buffers each corresponding to the at least one of the plurality of sense amps. The memory array arrangement thereby results in the plurality of word lines having reduced resistive and capacitive loading.