Flash Memory Biasing to Reduce Drain Stress
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Solution Overview
Problem
The existing biasing scheme in non-volatile memory devices, such as flash E2PROMs, leads to parasitic phenomena like Band to Band Tunneling and Stress Induced Leakage Current, which can damage the oxide layer and alter the state of memory cells, due to suboptimal voltage configurations during programming operations.
Innovation Solution
The proposed solution involves a non-volatile memory device with a matrix of memory cells where programming is achieved by applying a programming voltage to selected rows and a compensation voltage to unselected rows, while keeping unselected source lines floating, to reduce parasitic drain stress and prevent Band to Band Tunneling, thereby minimizing the generation of electron-hole pairs and Stress Induced Leakage Current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a positive voltage is applied to the bit line and a null voltage to the control gate during programming, then the selected memory cell can be programmed through Channel Hot Electron injection, but parasitic Band to Band Tunneling occurs in unselected memory cells causing drain stress and oxide layer damage
Solution Approach 1:
The patent applies a negative voltage to the substrate before and during the programming operation to create a preliminary counteracting electric field that prevents Band to Band Tunneling in unselected memory cells. This preliminary anti-action neutralizes the harmful parasitic effects before they can cause damage to the oxide layer, while still allowing the selected memory cell to be programmed through Channel Hot Electron injection.
Solution Approach 2:
The patent changes the substrate voltage parameter from null or positive to negative during programming operations. This parameter change fundamentally alters the electric field distribution in the device, suppressing parasitic tunneling currents in unselected cells while maintaining the ability to program selected cells. The negative substrate voltage becomes a controlling parameter that prevents harmful effects.
2Productivity
If the substrate is biased with a negative voltage to increase Channel Initiated Secondary Electron Injection efficiency, then programming efficiency improves, but parasitic Band to Band Tunneling and drain stress are exacerbated
Solution Approach 1:
The patent applies different voltage conditions to different regions of the device: the substrate is biased negatively to enhance CHE injection in selected memory cells, while simultaneously applying a positive voltage to the bit line creates a local electric field configuration that suppresses parasitic tunneling. This local quality differentiation allows the substrate to serve dual purposes - enhancing desired injection while suppressing harmful effects in different spatial regions.
Solution Approach 2:
The bit line voltage acts as an intermediary that mediates between the negative substrate bias and the programming operation. By applying a positive voltage to the bit line, it creates a local electric field that counteracts the parasitic tunneling induced by the negative substrate bias, thereby allowing the substrate to enhance CHE injection without causing excessive drain stress.
3Reliability
If unselected memory cells are subjected to positive drain voltage and null control gate voltage, then Band to Band Tunneling generates electron-hole pairs for parasitic drain stress, but applying compensation voltages increases device complexity
Solution Approach 1:
The patent segments the voltage control into distinct functional components: substrate voltage control for CHE injection enhancement, bit line voltage control for parasitic suppression, and source line voltage control for additional protection. This segmentation allows each voltage source to perform its specific function independently, simplifying the overall control logic while maintaining comprehensive protection against parasitic effects.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces parasitic drain stress and prevents unwanted charge injections, ensuring the integrity of memory cell states by maintaining a positive voltage difference between control gates and channels, thus minimizing damage to the oxide layer and maintaining accurate data storage.
Implementation Method 1
The transistor is programmed by injecting an electric charge into its floating gate, exploiting a physical phenomenon known as Channel Hot Electron (CHE) injection
Implementation Method 2
Consequently, a lateral electric field occurs between the drain and the source of the selected transistor; such lateral electric field is capable to energize (or 'heat') the electrons that are present in its channel. Moreover, also a transversal electric field occurs between the channel and the control gate of the selected transistor
Implementation Method 3
Each one of the corresponding transistors is in an electrical condition favorable for the occurrence of a physical phenomenon known as Band to Band Tunneling (BBT). According to such phenomenon, electron-hole pairs are generated at the reverse biased drain/substrate junction by electron tunneling
Implementation Method 4
in this case the holes generated by the BBT phenomenon are injected into the oxide layer, which is thus subjected to an excessive stress that may result in a critical damage thereof; in turn, this provokes the generation of an anomalous Stress Induced Leakage Current (SILC)
Data Source
AI summary
A memory device includes a matrix of memory cells arranged in a plurality of rows and a plurality of columns, each memory cell including a transistor having a first conduction terminal, a second conduction terminal and a control terminal; a plurality of bit lines each one associated with a column, each transistor of the column having the first conduction terminal coupled with the associated bit line; a plurality of first biasing lines each one associated with a row, each transistor of the row having the control terminal coupled with the associated first biasing line; a plurality of second biasing lines each one associated with at least one row, each transistor of the at least one row having the second conduction terminal coupled with the associated second biasing line; and means for programming at least one selected memory cell belonging to a selected row. The means for programming includes first biasing means for applying a programming voltage at least to a selected first biasing line associated with the selected row, and second biasing means for applying a program enabling voltage to a selected second biasing line associated with the selected row, each memory cell being programmed only when receiving both the programming voltage and the program enabling voltage.