Flash Memory Erase Method Managing Bit Line Leakage
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Solution Overview
Problem
Conventional methods for erasing flash memory sectors are inefficient and prone to deep over-erase, particularly due to the need for repeated erase pulses and extensive verification processes, which can lead to unnecessary wear and tear on memory cells.
Innovation Solution
A method that uses flags to identify and manage bit line leakage, employing slow program and verification processes to repair leaky sectors only when necessary, reducing the frequency of erase verification and eliminating the need for multiple address counters, thereby preventing deep over-erase and optimizing the erase process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an address counter is assigned to each memory sector to track verification addresses, then deep over-erase is prevented, but layout space is significantly occupied
Solution Approach 1:
The patent segments the flash memory into multiple groups, with each group having its own address counter. This allows tracking of verification addresses at the group level rather than requiring individual counters for every sector, reducing the total number of counters needed while still preventing deep over-erase within each group.
Solution Approach 2:
The patent introduces a group-level abstraction dimension, organizing sectors into groups and managing address counters at the group level. This dimensional change allows efficient tracking without requiring a counter for every individual sector, solving the space vs. reliability contradiction.
2Reliability
If erase verification is performed after every erase pulse, then erase completeness is ensured, but erase time is significantly increased
Solution Approach 1:
The patent implements periodic verification by performing erase verification only after a predetermined number of erase pulses have been applied to a group, rather than after every single erase pulse. This periodic approach ensures eventual erase completeness while dramatically reducing the total verification time and overhead.
Solution Approach 2:
The patent applies a predetermined number of erase pulses as a preliminary action before performing verification. This approach assumes that a sufficient number of pulses will achieve erasure, and verification is only needed to confirm completion, rather than verifying after each pulse.
3Reliability
If soft program is performed repeatedly to fix leaking sectors, then bit line leakage is corrected, but total erase time increases significantly
Solution Approach 1:
The patent performs soft program as a preliminary action to fix bit line leakage before applying erase pulses to the group. By correcting leaking sectors in advance, the patent prevents repeated soft program operations during the erase process, thereby reducing total erase time while maintaining reliability.
Data Source
AI summary
A method for erasing a flash memory group is provided, which comprises the following steps. (a) Apply a erase (ERS) pulse to a first subset of the group. (b) Perform one of a soft program verification (SPGMV) and a tight soft program verification (TSPGMV) on the first subset of the group. (c) Repeat steps (a) and (b) until a first predetermined condition is true. (d) Perform an erase verification (ERSV) on a second subset of the group. (e) Repeat steps (a) to (d) until a second predetermined condition is true. And (f) fix bit line leakage in a third subset of the group with a slow program (SLPGM) and apply an ERS pulse to the third subset.