Non-Volatile Memory Selection Device Programming with Parasitic Mitigation
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Solution Overview
Problem
Non-volatile memory circuits face challenges in programming threshold voltages due to parasitic devices, which can lead to improper programming and reduced yield, as conventional techniques often falsely detect threshold voltages of parasitic devices instead of the intended selection gates, affecting both affected and unaffected selection gates.
Innovation Solution
The implementation of a two-step program-and-verify operation with different threshold voltages and sense times for selection devices adjacent and non-adjacent to parasitic devices, where the control circuit sets a higher threshold voltage for devices adjacent to parasitic devices and uses a longer sense time for initial programming followed by a shorter sense time for fine-tuning, allowing proper programming while minimizing the impact on unaffected devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional programming techniques are used for selection gates, then programming speed is maintained, but measurement precision deteriorates due to false detection of parasitic device threshold voltages
Solution Approach 1:
The programming operation is divided into two distinct steps: a first programming step that programs all selection gates uniformly, and a second programming step that applies additional programming only to selection gates adjacent to parasitic devices. This segmentation allows precise targeting of affected devices without repeatedly programming all selection gates, thereby improving measurement precision while maintaining programming productivity.
Solution Approach 2:
The first programming step is performed as a preliminary action before the second step, establishing a baseline threshold voltage for all selection gates. This preliminary programming ensures that even if false detection occurs during initial verification, the selection gates have already been partially programmed, allowing the second step to focus only on correcting specific affected gates rather than re-programming all gates.
2Manufacturing precision
If uniform programming is applied to all selection gates, then device complexity is minimized, but manufacturing precision deteriorates due to improper programming of gates adjacent to parasitic devices
Solution Approach 1:
The programming approach transitions from uniform quality across all selection gates to local quality where different programming treatments are applied based on location. Selection gates adjacent to parasitic devices receive an additional second programming step with verified threshold voltages, while other selection gates maintain their threshold voltages from the first step. This local differentiation ensures manufacturing precision for critical gates without unnecessarily complicating the programming of all gates.
Solution Approach 2:
The method implements feedback through verification operations that measure threshold voltages after programming. The verification results feed into the decision-making process for the second programming step, allowing the system to identify which selection gates require additional programming. This feedback mechanism ensures that only gates with improperly programmed threshold voltages (likely due to parasitic device interference) receive additional programming, improving manufacturing precision while controlling complexity.
3Reliability
If selection gates are programmed with higher threshold voltages to overcome parasitic devices, then reliability improves, but use of energy increases due to additional programming operations
Solution Approach 1:
The method applies partial action by performing the second programming step only for selection gates adjacent to parasitic devices rather than all selection gates. This selective approach ensures that gates requiring higher threshold voltages for reliability receive the additional programming, while other gates maintain their energy-efficient single-step programming. The verification process identifies which gates need the excessive action of second programming, optimizing the balance between reliability and energy consumption.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively mitigates the effects of parasitic devices, enabling the use of non-volatile memory circuits that would otherwise fail testing, thereby improving manufacturing yield and ensuring proper operation of selection gates in non-volatile memory strings.
Implementation Method 1
A selection device coupled to the bit line may be configured to control conduction in a portion of the channel
Implementation Method 2
A control circuit may be configured to program the selection device by way of a programming operation
Implementation Method 3
program the selection device using an initial sense time and subsequent to programming the selection device using the initial sense time, program the selection device using another sense time shorter than the initial sense time
Data Source
AI summary
Non-volatile memory strings may include multiple selection devices for coupling memory cell devices to a bit line. Different programming operations may be used to program various individual selection devices in a non-volatile memory cells string. For example, a control circuit may set a threshold voltage of a particular selection device to a value greater than a threshold voltage of another selection device. In another example, the control circuit may program the selection device using an initial sense time. Subsequent to programming the selection device using the initial sense time, the control circuit may program the selection device using a different sense time that is shorter than the initial sense time.