Sense Amplifier Mapping for Non-Volatile Memory Peripheral Area Reduction
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Solution Overview
Problem
Current semiconductor memory systems face challenges in reducing the area required by peripheral circuitry, which hinders the miniaturization and performance enhancement of non-volatile memory devices, particularly in 3D stacked memory arrays.
Innovation Solution
Implementing improved mapping and control schemes for data transfer between sense amplifier circuitry and memory cache circuitry, utilizing a configuration with M-tier sense amplifiers and N-tier data latches, where M is less than N, to optimize data path circuitry and control signals, thereby reducing the spatial requirements of peripheral circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If traditional 1:1 mapping between sense amplifier tiers and data latch tiers is used, then data transfer control is simplified, but peripheral circuitry area is increased
Solution Approach 1:
The patent transitions from a traditional 1:1 tier mapping to an M:N tier mapping where M (sense amplifier tiers) is less than N (data latch tiers). This dimensional change in the mapping relationship allows multiple data latch tiers to share fewer sense amplifier tiers, reducing the overall peripheral circuitry area while managing complexity through hierarchical control structures.
Solution Approach 2:
The patent merges multiple data latch tiers under a single sense amplifier tier by implementing shared control logic and data paths. This consolidation reduces the total number of independent circuit blocks needed, thereby decreasing peripheral circuitry area while maintaining functional separation through logical control mechanisms.
2Productivity
If more sense amplifier tiers are used, then data transfer capability is improved, but chip area is increased
Solution Approach 1:
The patent implements multi-functionality by allowing sense amplifier tiers to serve multiple data latch tiers simultaneously. Each sense amplifier tier is designed to handle data transfer operations for multiple corresponding data latch tiers, increasing data transfer capability without proportionally increasing the number of sense amplifier tiers and thus limiting chip area growth.
3Area of stationary object
If M-tier sense amplifiers and N-tier data latches are used with M<N, then peripheral circuitry area is reduced, but data path circuitry complexity is increased
Solution Approach 1:
The patent segments the data transfer function into hierarchical levels: sense amplifier tiers handling higher-level data operations and data latch tiers handling lower-level storage operations. This segmentation allows the M:N mapping to reduce area while distributing complexity across different hierarchical levels rather than concentrating it in a single layer.
Solution Approach 2:
The patent introduces intermediary control structures that mediate between the reduced number of sense amplifier tiers and the larger number of data latch tiers. These intermediary elements manage the increased data path complexity by providing standardized interfaces and control protocols that simplify the overall system architecture despite the M<N mapping.
Data Source
AI summary
A data storage includes a memory array including a plurality of memory cells, and peripheral circuitry disposed underneath the memory array. The peripheral circuitry includes an M-tier sense amplifier (SA) circuit including X stacks of SA latches, wherein each SA latch is respectively coupled to a bit line of a memory cell of the plurality of memory cells; and an N-tier memory cache data (XDL) circuit including Y stacks of XDL latches, wherein M is less than N, and X is greater than Y. The peripheral circuitry further includes data path circuitry coupling (i) each SA latch of the X stacks of SA latches to (ii) a respective XDL latch of the Y stacks of XDL latches.