Memory Device Programming Speed and Reliability via Conditional Verify
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Solution Overview
Problem
Existing memory device programming techniques often result in programming errors due to skipping the final verify step, leading to undetected errors and data loss, especially in defective memory blocks, and incur a significant time penalty with additional read operations to correct these errors.
Innovation Solution
Implementing a method where the memory device intelligently determines whether to skip the final verify step based on predetermined thresholds for the number of programming loops, ensuring that memory cells are properly verified before completing programming, thereby reducing errors without the need for time-consuming enhanced post-write read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the final verify step is skipped to improve programming time, then programming speed is improved, but programming reliability deteriorates due to undetected errors in defective memory blocks
Solution Approach 1:
The patent applies dynamics by making the verify step conditional rather than static. The control circuit dynamically adjusts whether to perform the final verify step based on real-time monitoring of programming loop counts and data state transition patterns. For normal memory blocks, verify is skipped to maintain speed; for defective blocks showing abnormal programming behavior, verify is automatically performed to ensure reliability.
Solution Approach 2:
The patent implements feedback mechanisms where the control circuit continuously monitors programming loop counts and data state transitions during the programming process. This feedback information is used to determine whether the memory block is defective and whether the final verify step should be performed, creating a closed-loop control system that adapts to actual programming conditions.
2Reliability
If enhanced post-write read operations are conducted to detect programming errors, then programming reliability is improved, but programming time increases significantly
Solution Approach 1:
The patent applies preliminary action by performing error detection during the programming process itself through conditional verify steps, rather than conducting separate post-write read operations afterward. By integrating the verify function into the programming flow and executing it only when needed based on detected anomalies, the system prevents errors rather than detecting them after the fact, eliminating the time penalty of post-programming verification.
3Manufacturing precision
If verify is performed in every programming loop to ensure accuracy, then programming precision is improved, but programming speed deteriorates
Solution Approach 1:
The patent applies partial action by performing verify operations only partially - specifically, only in the final programming loop and only when defective block conditions are detected. For the majority of programming loops and for normal memory blocks, verify is omitted entirely. This selective approach provides sufficient verification to catch errors in defective blocks while maintaining high throughput for normal operation.
Data Source
AI summary
A memory device including an array of memory cells arranged in a plurality of word lines is provided. A control circuitry is configured to program the memory cells of a selected word line to a plurality of leading data states in a plurality of programming loops that include programming and verify pulses. The control circuitry is also configured to count a total number of programming loops during programming of the selected word line. The control circuitry is also configured to program at least one memory cell of the selected word line to a last data state in at least one last data state programming loop. In response to both the total number of programming loops being less than a first predetermined threshold and the number of last data state programming loops being equal to a second predetermined threshold, the control circuitry automatically skips verify in a final programming loop.