Split Block Row Decoding for NAND Flash Memory Arrays
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Solution Overview
Problem
The challenge in NAND flash memory devices is to maintain efficient row decoding circuitry as the reduced row pitch in vertically stacked memory blocks limits the layout of surrounding circuits, increasing design complexity and costs due to non-uniform wiring lengths and pitch matching issues.
Innovation Solution
A split block row decoding scheme is implemented, where a first decoding logic selects super blocks and a second decoding logic selects individual memory blocks within these super blocks, using discharge devices to manage signal lines and high voltage level shifters to ensure efficient voltage levels, allowing for a simplified layout and consistent signal line lengths across memory blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If vertically stacked memory blocks are used to increase cell density, then cell density is improved, but row pitch is reduced which limits the layout of surrounding circuits
Solution Approach 1:
The patent divides the memory array into multiple groups of memory blocks, each group being accessible through a dedicated row decoding circuit. This segmentation allows each circuit to service a smaller subset of blocks with consistent row pitch, resolving the layout limitations imposed by reduced overall row pitch in vertically stacked configurations.
2Quantity of substance
If row decoding circuitry is designed for vertically stacked memory blocks, then cell density is improved, but wiring lengths become non-uniform increasing design complexity
Solution Approach 1:
The patent implements separate row decoding circuits for each group of memory blocks, where each circuit is optimized for its specific local region. This ensures that wiring lengths and pitch requirements are consistent within each local group, eliminating the non-uniform wiring issues that would arise from a single global decoding circuit serving all vertically stacked blocks.
3Length of moving object
If pitch-limited circuits are used to access memory blocks, then row pitch is reduced, but circuit layout becomes more difficult
Solution Approach 1:
By segmenting the memory array into groups with dedicated row decoding circuits, the patent allows each circuit to operate with a larger effective row pitch within its local region, making the circuit layout more manageable and easier to manufacture despite the reduced physical row pitch of the vertically stacked blocks.
Data Source
AI summary
A non-volatile memory device having a memory array organized into a plurality of memory blocks, having either planar memory cells or stacks of cells. Row decoding circuitry of the memory device is configured to select a group of the plurality of memory blocks in response to a first row address, and to select a memory block of the group for receiving row signals in response to a second row address. Row decoding circuitry associated with each group of memory blocks can have a row pitch spacing that is greater than a row pitch spacing of a single memory block and less than or equal to a total row pitch spacing corresponding to the group of memory blocks.