Cache Page Copy in Non-Volatile Memory Using Adaptive Programming

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Solution Overview

Problem

Current non-volatile memory technologies face challenges in achieving high capacity and performance, particularly in efficiently utilizing device resources for large block memory operations and addressing the Yupin Effect, which affects read accuracy due to cell-to-cell coupling.

Innovation Solution

The implementation of a cache page copy scheme using a minimum number of n+1 data latches per memory cell, allowing for efficient data relocation and read operations with compensation for adjacent word line data, enabling adaptive full-sequence programming and look-ahead correction to mitigate the Yupin Effect.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If a minimum number of n+1 data latches are used for cache page copy, then device resource utilization is improved and memory performance is enhanced, but the complexity of managing latch structures and coordinating programming operations increases

Engineering Contradiction:
Improvememory performanceVSAvoidlatch structure management
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent segments the data latching and programming operations into distinct phases: reading data into latches, processing code bits sequentially, and programming memory cells in an adaptive full-sequence manner. This segmentation allows efficient resource utilization while managing complexity through structured operation phases.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements preliminary actions by reading and latching data before all code bits are available, and starting programming operations with the available code bits. This allows the system to begin productive work early and continue in an adaptive full-sequence mode, improving overall memory performance while managing latch coordination systematically.

Inventive Principle:
Principle #10Preliminary action

2Speed

If adaptive full-sequence programming is implemented starting before all code bits are available, then programming speed is improved and data-processing time is hidden within programming time, but the precision and coordination of programming operations become more challenging

Engineering Contradiction:
Improveprogramming speedVSAvoidprogramming operation coordination
Core Design Contradiction:
SpeedVSDifficulty of detecting and measuring

Solution Approach 1:

The patent implements dynamic programming operations where the programming sequence adapts based on code bit availability. The system transitions from reading and latching to processing available code bits and programming memory cells in an adaptive full-sequence mode, allowing flexible coordination that improves speed while managing complexity through dynamic state transitions.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent ensures continuous useful action by overlapping data processing with programming operations. Code bits are processed and memory cells are programmed in an continuous adaptive full-sequence manner, hiding data-processing time within programming time and maintaining high utilization of programming resources throughout the operation.

Inventive Principle:
Principle #20Continuity of useful action

3Measurement precision

If look-ahead correction is applied to mitigate the Yupin Effect, then read accuracy is improved, but the number of additional read operations and processing steps increases

Engineering Contradiction:
Improveread accuracyVSAvoidprocessing steps
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent applies preliminary look-ahead correction by reading adjacent word line data before performing the main read operation. This preliminary action provides correction information in advance, allowing the system to compensate for the Yupin Effect and improve read accuracy while integrating the correction steps into the overall read流程 efficiently.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS7502255B2Method for cache page copy in a non-volatile memory
Publication Date: 2009.03.10 SANDISK TECHNOLOGIES LLC
  • US7502255B2 patent drawing
  • US7502255B2 patent drawing
  • US7502255B2 patent drawing

AI summary

A non-volatile memory and methods include cached page copying using a minimum number of data latches for each memory cell. Multi-bit data is read in parallel from each memory cell of a group associated with a first word line. The read data is organized into multiple data-groups for shuttling out of the memory group-by-group according to a predetermined order for data-processing. Modified data are returned for updating the respective data group. The predetermined order is such that as more of the data groups are processed and available for programming, more of the higher programmed states are decodable. An adaptive full-sequence programming is performed concurrently with the processing. The programming copies the read data to another group of memory cells associated with a second word line, typically in a different erase block and preferably compensated for perturbative effects due to a word line adjacent the first word line.