Non-volatile Memory Erasing Method for Leakage Current Prevention
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Solution Overview
Problem
Conventional erasing operations in non-volatile memory often result in over-erased memory cells, leading to incorrect programming results and leakage currents, which can be exacerbated by power failures or interruptions, necessitating additional post-programming operations to correct threshold voltages.
Innovation Solution
A method involving a first erasing operation with a verification step, followed by a second targeted erasing operation using specific hole injection methods (Fowler-Nordheim tunneling or band-to-band hot hole injection) to ensure all memory cells have threshold voltages below the target level, reducing the need for post-programming corrections and minimizing leakage currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a first erasing operation is performed on all memory cells to reduce threshold voltages below a first target voltage level, then most memory cells achieve the erased state, but some memory cells become over-erased with threshold voltages below a second target voltage level, causing leakage currents
Solution Approach 1:
The erasing operation is divided into two distinct stages: a first erasing operation that applies a first erasing pulse to reduce threshold voltages below a first target voltage level, and a second erasing operation that selectively applies a second erasing pulse only to memory cells that fail verification, reducing their threshold voltages below a second target voltage level. This segmentation allows the majority of memory cells to be erased efficiently in the first stage while preventing over-erasing through selective application in the second stage.
Solution Approach 2:
The first erasing operation intentionally reduces threshold voltages below the final target level (excessive action) to ensure all memory cells are erased, accepting that some may become over-erased. The verification operation then identifies over-erased cells, and the second erasing operation applies corrective action only to those specific cells to bring their threshold voltages to the appropriate range, converting the excessive action into a controlled process.
2Reliability
If multiple verification operations are performed to ensure all memory cells are properly erased, then over-erased cells can be identified and corrected, but the overall erasing time increases
Solution Approach 1:
The verification process is segmented into two distinct verification operations: a first verification operation that checks whether threshold voltages are below the first target voltage level, and a second verification operation that checks whether threshold voltages are below the second target voltage level. This segmentation allows for efficient identification of over-erased cells without requiring exhaustive verification of all cells at the final target level, reducing overall verification time while maintaining reliability.
3Reliability
If a post-programming operation is performed on over-erased memory cells to increase their threshold voltages, then leakage currents are prevented, but additional processing time and complexity are required
Solution Approach 1:
Instead of performing a post-programming operation to increase threshold voltages of over-erased cells (the conventional approach), this invention inverts the approach by applying a second erasing pulse to selectively reduce threshold voltages of memory cells that fail the first verification operation. This inverted approach prevents over-erasing before it occurs rather than correcting it after, simplifying the overall operation sequence while maintaining reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces the number of over-erased cells, narrows the distribution range of threshold voltages, and prevents leakage currents, even in the event of power disruptions, by selectively adjusting threshold voltages to precise levels, thus ensuring accurate programming and reading results.
Implementation Method 1
A first erasing operation is performed, including reducing a threshold voltage of each of a plurality of memory cells through a first erasing pulse
Implementation Method 2
A method involving a first erasing operation with a verification step, followed by a second targeted erasing operation using specific hole injection methods (Fowler-Nordheim tunneling or band-to-band hot hole injection)
Data Source
AI summary
A non-volatile memory device and a non-volatile memory erasing operation method is provided. The method includes the following. A first erasing operation is performed, including reducing a threshold voltage of each of a plurality of memory cells of the non-volatile memory through a first erasing pulse. A first verification operation is performed to confirm whether the threshold voltage of each of the memory cells is less than an erasing target voltage level. In response to at least one of the memory cells failing the first verification operation, a second erasing operation is performed. The second erasing operation includes selecting the at least one memory cell failing the first verification operation, and reducing the threshold voltage of the at least one memory cell to be less than the erasing target voltage level through a second erasing pulse.