Variable Resistance Memory Device Program Current Control
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Solution Overview
Problem
The program operation time in phase change memory devices is significantly prolonged due to the time required to prepare and stabilize the program current for memory cells, which hampers the overall performance of variable resistance memory devices.
Innovation Solution
A variable resistance memory device architecture that includes memory cells arranged at the intersection of word and bit lines, control logic to generate a command flag for program operations, and a write driver activated by this flag to efficiently supply program current to memory cells, thereby reducing the time needed for program current preparation and cell state change.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the program current is supplied to the memory cell using conventional control methods, then the memory cell state can be changed, but the program operation time is significantly prolonged due to current preparation and stabilization time
Solution Approach 1:
The write driver is activated in advance by a command flag generated from the program command, preparing the program current before it is actually needed for the memory cell operation. This preliminary activation reduces the preparation time of the program current during the actual program operation.
Solution Approach 2:
The control logic generates a command flag based on the program command, which then activates the write driver. This feedback mechanism ensures that the write driver is activated at the appropriate time, optimizing the program current supply timing and reducing overall program operation time.
2Productivity
If the program current supply process is simplified to reduce preparation time, then program performance improves, but control precision over the memory cell operation may be compromised
Solution Approach 1:
The command flag acts as an intermediary signal between the program command and the write driver activation. This intermediary mechanism maintains precise control over the program current supply timing while enabling the write driver to be activated in advance, thus improving program performance without sacrificing control precision.
Solution Approach 2:
The conventional direct control method is replaced with a signal-based control system using the command flag. This substitution allows for more precise and flexible control of the write driver activation timing, improving both program performance and control precision simultaneously.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the program time for variable resistance memory devices, enhancing their program performance by streamlining the process of current supply and state transition in memory cells.
Implementation Method 1
the time that it takes to supply a program current to the memory cell includes the time that it takes to prepare for the program current to be supplied to the memory cell and the time that it takes the state of the memory cell to be changed by the program current
Data Source
AI summary
A variable resistance memory device includes memory cells arranged at a region where word lines and bit lines cross each other, control logic configured to generate a command flag indicative of a program operation mode in response to a program command provided from an external device and configured to control the program operation of the memory cells based on the command flag and a write driver configured to be activated in response to the flag command and configured to supply a program current to the memory cells.