Floating Gate Memory Interpoly Charge Trapping Structure
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Solution Overview
Problem
Planar memory cells with dielectric charge trapping structures face challenges in erasing charge due to the presence of a large electric field, making them difficult to use in flash memory devices, as charge is easily injected into the interpoly dielectric but hard to remove.
Innovation Solution
The solution involves controlling program and erase operations by changing the charge density on the floating gate and the charge trapping dielectric layer, with the floating gate experiencing a larger magnitude of charge density change than the dielectric layer, using specific bias arrangements to manage voltage and duration for effective programming and erasing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a dielectric charge trapping structure is used in planar memory cells, then the device can be made planar with simple structure, but charge is easily injected into the interpoly dielectric during programming and becomes very difficult to remove during erasing
Solution Approach 1:
The interpoly dielectric is segmented into multiple distinct layers: a first dielectric layer adjacent to the floating gate, a second dielectric layer adjacent to the control gate, and a charge trapping layer positioned between them. This segmentation allows charge to be trapped in a dedicated layer rather than distributed throughout the entire interpoly dielectric, making erasure more effective by concentrating the charge removal process.
Solution Approach 2:
The charge trapping layer acts as an intermediary structure between the first and second dielectric layers. It specifically captures and holds charge during programming, and serves as the primary target for charge removal during erasing operations, thereby mediating the charge storage and release functions separately from the bulk interpoly dielectric.
2Productivity
If charge density on the floating gate is increased during programming, then program performance is improved, but charge leakage into the interpoly dielectric increases making erasing impractical
Solution Approach 1:
Different regions of the dielectric structure are assigned different functions with distinct properties. The first dielectric layer provides tunneling characteristics for charge injection, the charge trapping layer provides deep trap states for charge storage, and the second dielectric layer provides blocking characteristics. This local differentiation allows high charge density to be maintained in the floating gate during programming while preventing charge leakage into the bulk dielectric, and enables effective erasure by targeting the charge trapping layer specifically.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for practical and efficient erase and program performance in planar memory cells, maintaining a satisfactory threshold voltage shift and reducing charge leakage, thereby improving the usability of planar memory cells in flash memory devices.
Implementation Method 1
a charge trapping dielectric layer above the floating gate and above the channel region
Implementation Method 2
a first tunneling barrier structure disposed on the surface of the substrate above the channel region
Data Source
AI summary
A nonvolatile memory cell has a semiconductor substrate, a multilayer stack including a charge trapping layer over a floating gate, a top conductive layer, and circuitry controlling program and erase operations on the nonvolatile memory cell. The program and erase operations change a first charge density on the floating gate by a larger magnitude than a second charge density on the charge trapping dielectric layer.