CMOS Nonvolatile Memory Cell With Segmented Gates
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Solution Overview
Problem
Current non-volatile memory technologies, such as Flash memory, face challenges with slow read times due to high threshold voltage requirements in floating-gate transistors, which hinder multilevel storage and device optimization, while DRAM is volatile and requires frequent refresh.
Innovation Solution
Implementing CMOS-compatible non-volatile storage elements, such as Magnetoresistive Random Access Memory (MRAM) or Phase-change memory cells in series with access transistors, which allow for faster read times and non-volatile storage by reducing threshold voltage and enabling independent control of word line gates, facilitating quicker bit line current and similar read/write times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If floating-gate transistor regions are heavily doped to properly engineer write and erase operations, then write and erase functions are achieved, but threshold voltage becomes high (approximately 1V) which slows down read times
Solution Approach 1:
The patent divides the transistor gate into two separate gates: a control gate for write/erase operations and a select gate for read operations. This segmentation allows independent optimization of each gate's function, enabling the control gate to be heavily doped for write/erase while the select gate can have lower doping for faster read times.
Solution Approach 2:
The patent implements dynamic voltage control where the select gate voltage can be independently adjusted during read operations to optimize read speed, while the control gate maintains its heavy doping for write/erase operations. This dynamic control resolves the contradiction by adapting gate characteristics to operational requirements.
2Speed
If threshold voltage is reduced to improve read times, then read speed increases, but unintended disturbances occur in unselected nonvolatile memory cells
Solution Approach 1:
By separating the gate functions into control gate and select gate, the patent enables independent voltage control. The select gate can apply high voltage for fast read access to selected cells while the control gate remains at appropriate voltage levels to prevent disturbances in unselected cells, thus resolving the reliability issue.
Solution Approach 2:
The patent applies different voltage conditions locally to different gates based on operational needs. During read operations, the select gate receives high voltage for fast access while the control gate maintains lower voltage to protect unselected cells, achieving both speed and reliability.
3Speed
If current is increased to speed up bit line driving, then read time decreases, but more current is required which complicates device optimization
Solution Approach 1:
The patent segments the current path control by using separate select gate and control gate. The select gate can be optimized to provide high current for fast bit line driving during read operations, while the control gate structure and voltage control enable efficient current management to reduce overall power consumption.
Solution Approach 2:
The patent implements dynamic current control through independent gate voltage adjustment. During read operations, the select gate voltage is optimized to maximize current flow for fast bit line charging. During non-read operations, voltages are adjusted to minimize current consumption, resolving the contradiction between speed and energy use.
4Speed
If DRAM structure is used to achieve fast read and random access, then read speed and random access capability are improved, but volatility increases requiring frequent refresh
Solution Approach 1:
The patent merges the fast access characteristics of DRAM with the non-volatile storage capability of floating-gate transistors. The memory cell combines a DRAM access transistor for fast read/write operations with a floating-gate transistor for non-volatile storage, achieving both fast random access and data retention without refresh requirements.
Solution Approach 2:
The patent creates a multi-functional memory cell that provides both volatile-like fast access performance and non-volatile data retention. The combined transistor structure enables the same cell to perform rapid read/write operations while maintaining data without power, unifying the benefits of both DRAM and non-volatile memory.
Data Source
AI summary
Embodiments provide systems, methods, and apparatuses with a plurality of row lines and column lines arranged in a matrix, and at least one memory cell having an access transistor and a CMOS-compatible non-volatile storage element coupled to the access transistor in series. The CMOS-compatible non-volatile storage element includes a node and is configured to hold a charge corresponding to a n-bit binary value where n is an integer greater than 1. The access transistor has a word line gate coupled to a row line, a first node coupled to a column line, a second node coupled to a storage node, with the storage node connected to said node of the CMOS-compatible non-volatile storage element. Access circuitry coupled to the memory cell is configured to activate the memory cell and sense a resulting current corresponding to the n-bit binary value.