Semiconductor Memory Device Vertical Channel Select Line Control
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Solution Overview
Problem
Existing semiconductor memory devices with nonvolatile memory technology face challenges in achieving high write and read speeds while maintaining data integrity even when power is cut off.
Innovation Solution
A semiconductor memory device with a vertical channel structure is developed, featuring a lower stack with alternating interlayer insulating and conductive layers, cell plugs, an upper stack with additional interlayer insulating and conductive layers, drain select plugs, and a separation pattern that separates adjacent drain select plugs, enhancing the separation and control of select lines in the memory cell array.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a vertical channel structure is used to improve write and read speeds, then access speed is improved, but separation and control of select lines becomes more difficult
Solution Approach 1:
The gate electrode is segmented into multiple regions (first gate electrode region and second gate electrode region) separated by a separation pattern. This segmentation allows independent control of select lines while maintaining the vertical channel structure, resolving the contradiction between improved access speed and difficulty in select line control.
Solution Approach 2:
Different regions of the gate electrode are assigned different functions: the first gate electrode region controls the first select line while the second gate electrode region controls the second select line. This local differentiation enables precise control of select lines in the vertical channel structure, addressing the control difficulty while preserving speed advantages.
2Manufacturing precision
If select lines are separated to improve control precision, then select line control is improved, but device structure becomes more complex
Solution Approach 1:
The gate electrode is divided into distinct segments with a separation pattern between them, enabling precise control of individual select lines. This segmentation achieves high control precision while adding minimal structural complexity compared to conventional approaches.
Solution Approach 2:
The separation pattern is implemented in the horizontal dimension within the vertical channel structure, allowing select line differentiation without increasing vertical complexity. This dimensional approach maintains structural simplicity while achieving precise control.
Data Source
AI summary
A semiconductor memory device includes a lower stack in which a plurality of first interlayer insulating layers and first conductive layers are alternately stacked, a plurality of cell plugs penetrating the lower stack in a vertical direction, an upper stack in which a plurality of second interlayer insulating layers and at least one second conductive layer are alternately stacked on the lower stack, a plurality of drain select plugs penetrating the upper stack and overlapping the plurality of cell plugs, respectively, and a separation pattern penetrating the upper stack and disposed between at least two adjacent drain select plugs among the plurality of drain select plugs, wherein the at least two adjacent drain select plugs each have a semi-cylindrical shape and remaining drain select plugs except for the at least two adjacent drain select plugs among the plurality of drain select plugs each have a cylindrical shape.