Cache Memory in Non-Volatile Memory Transaction Path
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Solution Overview
Problem
Non-volatile memory in data processing systems consumes high energy and has slow read speeds, making it inefficient for use as execute-in-place memory due to the large energy required for reading data.
Innovation Solution
Incorporating a cache memory between the interconnect circuitry and non-volatile memory to cache data read from the non-volatile memory, thereby reducing the need for frequent, energy-intensive read operations and improving data access speeds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If non-volatile memory is used as execute-in-place memory, then data storage capacity is improved, but energy consumption increases and read speed decreases
Solution Approach 1:
The memory system is segmented into two distinct parts: non-volatile memory for bulk data storage and cache memory for frequently accessed data. This segmentation allows the system to maintain large storage capacity while reducing energy consumption for read operations by serving data from the smaller, energy-efficient cache when possible.
Solution Approach 2:
A cache memory is introduced as an intermediary component between the non-volatile memory and the processor. This intermediary buffer stores copies of frequently accessed data, reducing the frequency of direct reads from non-volatile memory and thereby lowering overall energy consumption while maintaining fast access speeds.
2Quantity of substance
If non-volatile memory is used as execute-in-place memory, then data storage capacity is improved, but operation speed decreases
Solution Approach 1:
The memory hierarchy is segmented into non-volatile memory for capacity and cache memory for speed. This segmentation enables the system to leverage the high storage capacity of non-volatile memory while using the faster cache memory to satisfy time-critical read operations.
Solution Approach 2:
Data is preliminarily loaded into the cache memory from non-volatile memory before being accessed by the processor. This preliminary action of pre-caching frequently accessed instructions and data ensures that subsequent reads occur at cache speeds rather than slower non-volatile memory speeds.
3Productivity
If cache memory is added between interconnect circuitry and non-volatile memory, then data access efficiency is improved, but device complexity increases
Solution Approach 1:
The cache memory is designed to work with the existing interconnect circuitry and memory architecture, serving multiple functions including data caching, address translation, and memory management. This multi-functionality justifies the added complexity by providing broad system benefits across different operational modes.
Data Source
AI summary
A data processing system includes interconnect circuitry providing a plurality of memory transaction paths between one or more transaction masters, including a processor, debugging circuitry and a DMA unit, and one or more transaction slaves including a non-volatile memory, a DRAM memory and an I/O interface. A cache memory is provided between the interconnect circuitry and the non-volatile memory. This cache memory may be a two way set associative cache memory. The cache memory may serve as a read-only cache memory. A cache miss will result in a line fill of a cache line including the target data which was missed. If prefetching is enabled for the cache memory and the transaction was attempting to read a program instruction, then a prefetch operation may be performed in which a further contiguous cache line of data is also fetched into the cache memory upon the cache miss.