Memory Architecture Accessing/Allocation TRIZ Cases
- Solid State Memory Power Management via Dynamic Configuration
A solid state memory system uses a power manager unit to alter non-volatile memory array configurations based on dynamic commands.
- Cache Memory in Non-Volatile Memory Transaction Path
Placing a cache memory between interconnect circuitry and non-volatile memory reduces energy consumption and increases read speed for program instructions.
- Cache Way Purge Control for Power and Coherency
Purge control circuit writes back modified data to main memory before stopping cache ways, preventing coherency issues while reducing power consumption.
- Firmware Memory Error Recovery via Poison Signature Cleansing
Firmware identifies and cleanses memory ranges with poison signatures, enabling safe reuse and preventing system crashes from non-correctable errors.
- Flash Memory Page Mapping for Write Speed
Dual mapping tables manage logical to physical page addresses, reducing data movement and write time during small updates.
- Processing Buffer Circuit for Offloaded Memory Data Operations
A processing buffer circuit executes data operations within a memory module using standard DDR interfaces.
- Ray Traversal Distance Testing Using Hit Point ID Tuples
A ray tracing apparatus uses hit point identifiers to disambiguate intersection order during distance testing.