Solid State Memory Power Management via Dynamic Configuration
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Solution Overview
Problem
High power consumption by modern SSDs in data centers and consumer devices poses challenges for energy efficiency, reliability, and performance, with existing solutions failing to effectively address these issues.
Innovation Solution
A solid state memory system with a power management mechanism that includes an interface circuit, device processor, non-volatile memory array, and power manager unit, which receives dynamic power limit commands to adjust operating configurations and update metadata logs, reducing power consumption by altering voltage levels and addressing memory segments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If high-performance SSDs with large DRAMs and high-performance CPUs are used to provide higher performance, then performance is improved, but power consumption increases significantly
Solution Approach 1:
The patent implements dynamic power management by allowing the SSD to switch between different power modes (performance mode and power-saving mode) based on operational requirements. The host system can issue power limit commands that dynamically adjust the SSD's operating state, enabling it to adapt its power consumption to match actual workload demands rather than operating at fixed high performance levels continuously
Solution Approach 2:
The patent changes operational parameters of the SSD including voltage levels, memory array configuration, and buffer management strategies. By adjusting these parameters dynamically based on power limit commands, the SSD can reduce power consumption while maintaining acceptable performance levels. Specific parameter changes include modifying voltage to memory cells, adjusting memory array configuration, and managing buffer cache usage
2Use of energy by moving object
If power consumption is reduced by altering operating configuration, then power usage decreases, but performance and capacity are traded off
Solution Approach 1:
The patent applies partial action by selectively powering down or reducing power to specific components or memory regions within the SSD rather than shutting down the entire device. This allows the system to reduce overall power consumption while maintaining essential functionality and performance for active workloads. The host can specify partial power limits that affect only certain operations or data regions
3Use of energy by moving object
If the memory array configuration is altered to meet power limits, then power consumption is controlled, but data access patterns and performance characteristics change
Solution Approach 1:
The patent uses buffer memory and metadata logging to prepare for and compensate for configuration changes. Before altering memory array configuration to meet power limits, the system uses the buffer to cache frequently accessed data and maintains metadata logs that track configuration states. This preliminary preparation ensures that data access remains efficient even when the underlying memory configuration changes
Solution Approach 2:
The buffer memory acts as an intermediary between the host and the memory array when power limits are imposed. It absorbs the impact of configuration changes by caching data and managing access patterns, thereby shielding the host from performance degradation. The metadata log also serves as an intermediary, tracking configuration states and enabling proper data retrieval regardless of memory array reconfiguration
Data Source
AI summary
A solid state memory system includes: an interface circuit; a device processor, coupled to the interface circuit, configured to receive a dynamic power limit command through the interface circuit and update a metadata log based on the dynamic power limit command; a non-volatile memory array coupled to the interface circuit; and a power manager unit, coupled between the device processor and the non-volatile memory array, configured to alter an operating configuration of the non-volatile memory array to meet the requirement of the dynamic power limit command.