Flash Memory Page Mapping for Write Speed
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Solution Overview
Problem
Conventional flash memory systems face performance issues due to the need for block-level erasure, leading to increased data movement and writing time, especially when updating small amounts of data, which affects the speed of data writing and overall system performance.
Innovation Solution
A data accessing method and controller system that utilize logical and physical page mapping tables to manage data access on a page-by-page basis, reducing data movement by directly writing to valid physical page addresses and updating mapping tables to optimize data writing speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If block-by-block writing mechanism is used in flash memory, then data can be written following conventional hard disk methods, but data movement increases and writing time is substantially increased when only small amounts of data need to be updated
Solution Approach 1:
The patent segments the flash memory address space into multiple blocks, where each block can be independently managed. Instead of treating the entire flash memory as a single block that must be erased and rewritten, the system divides it into smaller units that can be updated individually. This segmentation allows only the specific blocks containing updated data to be rewritten, rather than the entire data area, thereby reducing data movement and improving writing speed while maintaining compatibility with conventional block-level access methods.
2Reliability
If whole physical block is erased when updating data in a page, then flash memory erase operation requirements are met, but time for accomplishing the write operation is substantially increased
Solution Approach 1:
The patent implements preliminary action by maintaining a mapping table that tracks the correspondence between logical block addresses and physical block addresses before write operations occur. When data needs to be updated, the system consults the mapping table in advance to identify which physical blocks contain the data to be updated. This preliminary identification allows the system to erase only the specific physical blocks that need updating, rather than erasing entire data areas, thereby reducing write operation time while ensuring proper flash memory erase operation compliance.
3Ease of operation
If logical blocks are allocated according to physical block dimensions, then host system can access flash memory, but data moving movements increase when updating small amounts of data
Solution Approach 1:
The patent introduces a mapping table as an intermediary between the host system and the physical flash memory blocks. This mapping table stores the correspondence relationships between logical block addresses and physical block addresses. When the host system needs to update data, it provides the logical block address, and the mapping table quickly identifies the corresponding physical block address. This intermediary mechanism allows the host system to access flash memory using logical addresses while enabling precise identification of physical blocks that need updating, thereby reducing unnecessary data movement time while maintaining ease of operation.
Data Source
AI summary
A data accessing method for accessing data in a plurality of physical page addresses of a plurality of physical blocks in a flash memory chip is provided. The data accessing method includes proving a plurality of logical page addresses for a host system, creating a logical page to physical page mapping table and a physical page to logical page mapping table to record the mapping between the logical page addresses and the physical page addresses. The data accessing method also includes writing data into the physical page addresses, and updating the logical page to physical page mapping table and the physical page to logical page mapping table. The data accessing method further includes determining whether the physical page addresses are valid or invalid based on the logical page to physical page mapping table and the physical page to logical page mapping table.