Cache Way Purge Control for Power and Coherency
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Solution Overview
Problem
In cache memory systems, maintaining coherency between cache and main storage while reducing power consumption by stopping unused ways is challenging, as it often leads to data inconsistencies and inefficient processing due to old data being transferred back to the cache.
Innovation Solution
A processor with a cache memory system that includes a usage information register, purge control circuit, access control circuit, and power control circuit to manage the usage of cache ways, ensuring that data is properly written back to main storage and unused ways are powered down, preventing old data from being retransfered.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If ways are stopped to reduce power consumption, then power consumption is reduced, but data coherency between cache and main storage deteriorates
Solution Approach 1:
The patent applies preliminary action by writing back modified data to main storage before stopping the cache way. The purge control circuit identifies which data has been modified (dirty data) and ensures it is written back to main storage before the way is deactivated. This prevents data coherency issues by proactively handling the data migration before the cache way becomes inactive, thus resolving the contradiction between power reduction and data coherency maintenance.
2Reliability
If all ways are operated to maintain data coherency, then data coherency is maintained, but power consumption increases
Solution Approach 1:
The patent applies local quality by selectively managing individual cache ways rather than treating the entire cache uniformly. Each way can be independently monitored for modified data and selectively stopped based on its specific state. This allows the system to maintain data coherency only where necessary (in ways with modified data) while stopping other ways to reduce power consumption, thus resolving the contradiction between maintaining coherency and reducing power usage.
3Speed
If old data is transferred from main storage to cache before write-back completes, then cache access speed is improved, but data coherency deteriorates
Solution Approach 1:
The patent applies feedback by implementing a control mechanism that monitors the write-back status of data and uses this information to control cache access. The access control circuit receives feedback about which data has been written back to main storage and prevents access to data that has not yet been synchronized. This feedback-based control ensures that cache access speed is optimized while maintaining data coherency by blocking access only when necessary.
Data Source
AI summary
A processor includes an arithmetic processing circuit, a cache memory including a plurality of ways, a usage information register storing usage information indicating whether to use each of the plurality of ways, a purge control circuit performing purge processing on a basis of rewriting of the usage information within the usage information register according to an instruction executed by the arithmetic processing circuit, the purge processing including processing of deleting, from the cache memory, target data retained in a target way to be stopped and processing of writing back part of the target data, the part of the target data being data rewritten in the cache memory, to a main memory at a lower level than the cache memory, and an access control circuit controlling accessing the cache memory on a basis of a memory access request received from the arithmetic processing circuit and status of the purge processing.