Cache Memory Scheduler Segmentation for Scalable Queue Depth
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Solution Overview
Problem
The complexity of cache schedulers makes it difficult to increase the queue depth, which is a critical parameter determining the processing performance of cache memory devices, limiting scalability.
Innovation Solution
A cache memory device utilizing multiple cache schedulers with statistically identical memory access rates, allocated based on the number of memory accesses for each address, to maximize the queue depth and efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single cache scheduler is used with complex mechanisms, then cache scheduling functions are achieved, but the queue depth cannot be increased due to high complexity
Solution Approach 1:
The patent divides a single complex cache scheduler into multiple simpler cache schedulers (first cache scheduler and second cache scheduler). Each scheduler handles a portion of the cache memory, reducing the complexity of individual schedulers while collectively achieving the required queue depth through parallel operation of multiple schedulers.
2Adaptability or versatility
If multiple cache schedulers are introduced to increase queue depth, then scalability is improved, but device complexity increases
Solution Approach 1:
The cache memory is segmented into multiple regions, each managed by a dedicated cache scheduler. This segmentation allows the system to scale queue depth by adding more schedulers while keeping each scheduler's internal complexity manageable through consistent design patterns.
Solution Approach 2:
The patent changes the parameter of scheduler quantity from single to multiple, enabling queue depth scalability. By replicating the scheduler structure across multiple instances with standardized interfaces and management mechanisms, the system achieves scalability without proportionally increasing overall complexity.
3Productivity
If complex mechanisms are applied to enhance memory access efficiency, then cache hit-rate is improved, but the queue depth scalability is limited
Solution Approach 1:
The patent segments the cache memory into multiple ways or regions, each with its own scheduler instance. This segmentation allows complex memory access patterns to be distributed across multiple simpler scheduling units, maintaining high memory access efficiency through parallel processing while avoiding the need for a single overly complex scheduler.
Data Source
AI summary
It is one object of the present disclosure to provide measures for securing scalability of the queue depth of cache schedulers by utilizing a plurality of cache schedulers. To this end, a cache memory device in accordance with one embodiment of the present disclosure comprises: a request reception unit configured to receive input transactions; a traffic monitoring module configured to monitor traffic of the input transactions; N cache schedulers, wherein N is an integer greater than or equal to 2; a region setting module configured to set N input transaction regions corresponding to each of the N cache schedulers based on the traffic of the input transactions monitored, wherein input transactions are transferred via an input transaction region set in each cache scheduler; and an access execution unit configured to perform cache memory accesses to input transactions scheduled by the N cache schedulers.