Memory Adressing/Allocation/Relocation TRIZ Cases
- Flash File-System Data Restoration Through F2FS Metadata Mapping
Maps F2FS metadata in a file-system image to restore target files and improve digital evidence collection from flash storage.
- Nonvolatile Memory Read Voltage Calibration Across Temperature
A temperature-indexed voltage table helps non-volatile memory reduce erroneous data decisions without repeated shift reading.
- Multicore 3-D Graphics Memory Management for Ordered Rendering
Allocation lists and segmented virtual address ranges let GPU cores render primitives in parallel while preserving order and limiting memory overflow.
- Cache Freshness Validation Using a Guaranteed Clock
Traditional caches can return stale data; a guaranteed clock and database polling invalidate changed objects before responses are served.
- Adaptive Valley Voltage Detection for NAND Memory Reads
By sampling flipped bits across adjusted read voltages, the peripheral circuit identifies a valley voltage and improves data retrieval accuracy in NAND cells.
- Volatile Storage in NAND Memory Using Defective Cell Strings
Defective NAND cell strings can be repurposed for volatile storage while other strings retain non-volatile data, adding capacity without extra circuit real estate.
- Chalcogenide Memory Bank Buffer for Read Endurance
A bank buffer stores read results and reuses them for matching addresses, reducing repeated reads that stress chalcogenide memory cells.
- Storage Controller Memory Switching for On-Device LLMs
Dynamic switching between auxiliary-memory loading and host access helps run large language models on constrained devices.
- Memory Component Sub-Row Writes Without Pre-Write Sensing
Writing complete memory sub-rows directly to sense amplifiers removes pre-write sensing, reducing power use and access time.
- Processor Cache Eviction by Memory Reuse to Reduce DRAM Traffic
Reuse-based eviction priorities retain frequently accessed data in processor cache, reducing DRAM traffic, power use, and latency.
- Routing Circuit Modulo-Division Mapping for Non-Power-of-Two Topologies
Modulo-n and div-n operations map address bits to non-power-of-two topology dimensions, preventing routing holes and aliasing.
- Store Buffer Allocation Through Duplicate Data Sharing
Duplicate store-data portions share one data-buffer entry, expanding effective capacity without increasing hardware size, power, or circuit area.
- Memory Read Accuracy via Adjacent Reference-Cell State
Dense memory cells can suffer interlayer interference; an adjacent reference cell sets sensing-node discharge time to improve target-cell read accuracy.
- Near-Memory Units for Directional Blocked Data Quantization
Processing-in-memory arithmetic units quantize BFloat16 data into directional blocked formats, reducing CPU-memory movement and energy demands.
- DRAM Column Page Mode for Lower-Latency Matrix Access
Multiple row activations make DRAM column reads slow and power-hungry; column page mode activates selected MATs concurrently.
- Removable Memory Device Current Classes for Multiple Voltage Types
Multiple power voltages complicate host-side configuration; current-consumption classes keep each supply within its permissible current limit.
- In-Memory Telemetry Processor for Latency and Bandwidth Tracking
A dedicated processor inside the memory subsystem measures bandwidth and smooths latency statistics locally, avoiding host data movement that adds delay and energy use.
- Memory System Read-Retry Voltage Control for Multi-Bit Cells
Threshold-voltage counts select mapped read-retry offsets, helping multi-bit memory cells avoid read errors without exhaustive voltage trials.
- NAND Flash Memory Adaptive Read Voltage Control
The controller counts higher-state memory cells and shifts read voltage on-chip to improve NAND flash retrieval and reduce errors.
- Peripheral Device Resource Isolation for Untrusted Hosts
Hidden metadata lets a peripheral command processor dynamically enforce ownership, preserving secure execution on untrusted hosts.
- Data Storage Bit-Width Selection With Blockwise Differentials
Blockwise differential values replace absolute effective bit numbers to reduce storage width for large index-data sets.
- Shared-Storage Cache Design for Parallel Miss Handling
Dual-port FPGA SRAM shares cache data and miss information while separate request and response pipelines reduce contention.
- BMC Memory Expansion Through External Memory Proxying
Fixed BMC hardware can limit service growth; a memory agent reserves external subsystem memory through a computing-device proxy.
- Memory Controller Compression for Multilevel Threshold Voltage Storage
Multilevel-cell threshold voltage values are compressed into vectors to reduce memory-region overload while limiting decompression errors.
- Out-of-Order Wordline Programming for Per-Unit P2L Mapping
Deferring the first wordline lets each physical unit store P2L mappings in non-volatile memory, simplifying power-loss handling.