Volatile Storage in NAND Memory Using Defective Cell Strings
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Solution Overview
Problem
Traditional NAND memory architectures face challenges in efficiently utilizing defective memory cells for volatile storage, leading to increased demands on circuit real-estate and complexity in operations such as selective slow programming convergence and multi-level inhibit modes.
Innovation Solution
Repurpose blocks of memory cells deemed unsuitable for non-volatile storage for volatile storage, allowing flexible operation between volatile and non-volatile modes, and prohibit storage of non-volatile data in defective series-connected memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional NAND memory architectures are used to store volatile data, then data storage capacity is increased, but circuit real-estate demands and operational complexity increase
Solution Approach 1:
The patent enables NAND memory blocks to serve dual purposes: non-volatile storage mode and volatile storage mode. By configuring blocks as volatile memory using simple control logic that monitors write operations and prevents erases, the same physical infrastructure provides both volatile and non-volatile storage capabilities, eliminating the need for separate volatile memory circuits and reducing overall device complexity
Solution Approach 2:
The patent extracts volatile storage functionality from traditional separate volatile memory circuits and implements it within the NAND memory blocks themselves. By designating specific blocks as volatile memory and using control logic to manage write/erase operations, the solution removes the need for additional volatile memory circuitry while maintaining the required functional capabilities
2Quantity of substance
If defective memory cells are used for volatile storage, then storage capacity is optimized, but reliability of non-volatile storage decreases
Solution Approach 1:
The patent segments the NAND memory array into distinct blocks that can be independently configured as either volatile or non-volatile storage. This segmentation allows defective blocks to be designated as volatile memory while preserving intact blocks for reliable non-volatile storage, thereby optimizing overall storage capacity utilization without compromising the reliability of the non-volatile portion
Solution Approach 2:
The patent applies local quality by assigning different functional characteristics to different blocks within the same memory array. Blocks designated for volatile storage can tolerate defects that would be unacceptable in non-volatile blocks, as the control logic prevents erase operations that would affect data integrity. This localized functional differentiation allows each block to be optimized for its specific purpose
3Manufacturing precision
If selective slow programming convergence and multi-level inhibit modes are implemented, then programming precision is improved, but device complexity increases
Solution Approach 1:
The patent extracts the complex programming control functions from the volatile memory blocks and relocates them to the control logic in the peripheral circuitry. This extraction allows the volatile memory blocks to operate with simple write/erase control while the sophisticated programming precision features are handled by the dedicated control logic, thereby reducing the operational complexity of the memory blocks themselves
Data Source
AI summary
Memories might include an array of memory cells having a plurality of strings of series-connected memory cells and a controller configured to cause to memory to access a first string of series-connected memory cells of the plurality of strings of series-connected memory cells in a first mode of operation for volatile storage of data to the first string of series-connected memory cells, and access a second string of series-connected memory cells of the plurality of strings of series-connected memory cells in a second mode of operation for non-volatile storage of respective data to each memory cell of a plurality of memory cells of the second string of series-connected memory cells