Store Buffer Allocation Through Duplicate Data Sharing
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Solution Overview
Problem
The available capacity of the store buffer in data processing systems becomes a bottleneck due to frequent store operations, leading to stalling, and increasing the buffer size to alleviate this issue increases power consumption and circuit area.
Innovation Solution
The allocation circuitry identifies and represents duplicate data portions using a single data entry, effectively increasing the capacity of the store buffer without the need for larger hardware, by setting multiple indications to identify the duplicate data entry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the store buffer size is increased to handle frequent store operations, then the store operation throughput is improved, but the power consumption and circuit area increase
Solution Approach 1:
The patent merges duplicate data portions into a single data entry in the store buffer. When multiple store operations contain identical data, the allocation circuitry identifies these duplicates and represents them using a single data entry with multiple address buffer entries pointing to it. This consolidation reduces the number of data entries required, thereby reducing power consumption and circuit area while maintaining the ability to handle frequent store operations.
Solution Approach 2:
The patent makes a single data entry serve multiple functions by allowing it to represent multiple duplicate data portions. The data entry is shared across multiple address buffer entries through the indication mechanism, enabling one data entry to fulfill the role of multiple entries would otherwise be needed. This multi-functionality increases effective buffer capacity without proportionally increasing hardware resources.
2Productivity
If the store buffer size is increased to handle frequent store operations, then the store operation throughput is improved, but the circuit area increases
Solution Approach 1:
The patent merges duplicate data portions into a single data entry in the store buffer. When multiple store operations contain identical data, the allocation circuitry identifies these duplicates and represents them using a single data entry with multiple address buffer entries pointing to it. This consolidation reduces the number of data entries required, thereby reducing power consumption and circuit area while maintaining the ability to handle frequent store operations.
Solution Approach 2:
The patent makes a single data entry serve multiple functions by allowing it to represent multiple duplicate data portions. The data entry is shared across multiple address buffer entries through the indication mechanism, enabling one data entry to fulfill the role of multiple entries would otherwise be needed. This multi-functionality increases effective buffer capacity without proportionally increasing hardware resources.
3Use of energy by stationary object
If the store buffer capacity is limited, then the power consumption and circuit area are reduced, but store operations must stall
Solution Approach 1:
The patent uses indications in the address buffer to create logical copies of data entry references. Instead of physically copying data, the system creates multiple pointers (indications) that reference the same data entry. This allows the same physical data to be logically replicated across multiple store operations without requiring additional physical storage space, thereby preventing stalls while maintaining low power consumption and circuit area.
Solution Approach 2:
The patent merges duplicate data portions into a single data entry in the store buffer. When multiple store operations contain identical data, the allocation circuitry identifies these duplicates and represents them using a single data entry with multiple address buffer entries pointing to it. This consolidation reduces the number of data entries required, thereby reducing power consumption and circuit area while maintaining the ability to handle frequent store operations.
4Area of stationary object
If the store buffer capacity is limited, then the circuit area is reduced, but store operations must stall
Solution Approach 1:
The patent uses indications in the address buffer to create logical copies of data entry references. Instead of physically copying data, the system creates multiple pointers (indications) that reference the same data entry. This allows the same physical data to be logically replicated across multiple store operations without requiring additional physical storage space, thereby preventing stalls while maintaining low power consumption and circuit area.
Solution Approach 2:
The patent merges duplicate data portions into a single data entry in the store buffer. When multiple store operations contain identical data, the allocation circuitry identifies these duplicates and represents them using a single data entry with multiple address buffer entries pointing to it. This consolidation reduces the number of data entries required, thereby reducing power consumption and circuit area while maintaining the ability to handle frequent store operations.
Data Source
AI summary
Apparatuses, systems, methods, computer-readable media, and computer code are disclosed. An apparatus comprises allocation circuitry configured to allocate store data comprising N portions in a store buffer. The store buffer comprises a data buffer configured to hold data entries, each data entry configured to hold one of the N portions of the store data; and an address buffer configured to hold address entries, wherein a given address entry is indicative of a memory address at which the store data is to be stored and is associated with N indications identifying one or more of the data entries that contain the store data. The allocation circuitry is responsive to a determination that M portions of the N portions of the store data each comprise duplicate data to set M indications of the N indications to identify a given data entry holding the duplicate data.


