Shared-Storage Cache Design for Parallel Miss Handling
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Solution Overview
Problem
Existing cache systems face challenges in efficiently managing memory-access locality and resource allocation for cache data and cache-miss information, leading to potential waste or performance degradation due to improper configuration of miss status holding registers.
Innovation Solution
A cache-designing method where cache entries and MSHR entries share the same storage space, utilizing dual-port SRAMs in an FPGA to create parallel pipelines for request and response processing, overcoming pipeline contention and adapting to different access characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If separate storage spaces are used for cache data and cache-miss information, then resource allocation is simplified, but storage resources are wasted and performance degrades due to improper configuration of miss status holding registers
Solution Approach 1:
The patent merges the storage spaces for cache data and cache-miss information into a single shared storage space. The cache controller dynamically manages this shared space, allocating portions for cache data and portions for cache-miss information based on actual workload requirements. This merging eliminates the need for separate dedicated storage spaces, thereby reducing total storage resource consumption while maintaining the ability to adapt to different memory-access locality patterns through dynamic allocation.
Solution Approach 2:
The shared storage space is designed to serve multiple functions: it can store cache data when the workload exhibits good locality, and it can store cache-miss information when the workload requires extensive miss handling. The cache controller determines the appropriate function for each entry based on the current operational context, making the storage system universal and adaptable to varying workload characteristics without requiring separate specialized storage structures.
2Productivity
If large-capacity MSHR array is used, then performance gain is achieved for applications with limited memory-access bandwidth, but static storage resources are consumed
Solution Approach 1:
Instead of using a large fixed-capacity MSHR array that consumes static storage resources, the patent implements a dynamic allocation mechanism within a shared storage space. The cache controller can dynamically adjust the number of entries available for cache-miss information based on the current workload's memory-access patterns. This dynamic approach allows the system to achieve high throughput for workloads requiring large MSHR capacity while only allocating the necessary storage resources at any given moment, rather than provisioning for the maximum possible capacity statically.
3Quantity of substance
If cache entries and MSHR entries share the same storage space, then storage resources are utilized efficiently, but pipeline contention may occur
Solution Approach 1:
The cache controller acts as an intermediary that manages access to the shared storage space between cache data operations and cache-miss information operations. It mediates potential pipeline contention by coordinating read and write operations, ensuring that cache data access and cache-miss information access do not conflict. This intermediary management layer handles the complexity of shared space access, allowing efficient resource utilization while preventing pipeline stalls that would arise from uncoordinated access to the same storage resources.
Data Source
AI summary
A cache-designing method using cache lines to record cache-miss information is provided, wherein cache lines and cache-miss information are stored in a common storage space by means of shared storage. Tags of cache lines, as well as cache lines and cache-miss information, are stored separately in different static random-access memories, wherein multiple independent memories are used for tags, while a single memory is for cache lines and cache-miss information. A request-processing pipeline and a response-processing pipeline are constructed to be parallelable and used respectively for processing memory-access requests and for processing memory-response data. As compared to existing non-blocking cache designs that support plenty of miss status holding registers, the present disclosure allows storage sharing between cache data and cache-miss information, and leverages dual-port feature of static random-access memories in FPGA, so as to design separate pipelines to achieve memory access respectively for memory-access request processing and for memory-response data processing.