In-Memory Telemetry Processor for Latency and Bandwidth Tracking

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Solution Overview

Problem

Existing memory sub-systems face challenges in processing high-bandwidth telemetry data efficiently, leading to increased latency, reduced bandwidth, and high energy consumption due to the need for data movement between the host processor and memory modules, which general-purpose processors exacerbate with unpredictable delays.

Innovation Solution

Implementing a specialized memory telemetry processor within the memory sub-system to process telemetry data in real-time without transmitting it to the host system, utilizing a dedicated processor for tasks like prefetch predictions, data compression, and anomaly detection directly within the memory module.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If telemetry data is processed by the host processor, then processing capability is provided, but latency increases and bandwidth decreases due to data movement requirements

Engineering Contradiction:
Improvetelemetry processing capabilityVSAvoidlatency
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent extracts the telemetry processing function from the host processor and relocates it to a dedicated processor within the memory module. This separation allows telemetry data to be processed locally without requiring transmission to the host processor, thereby reducing latency while maintaining processing capability.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent introduces a dedicated processor as an intermediary component within the memory module that handles telemetry processing. This intermediary processor performs functions such as prefetch predictions, data compression, and anomaly detection locally, eliminating the need for data to travel to the host processor for processing.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If telemetry data is transmitted to the host processor for processing, then processing functions are available, but energy consumption increases

Engineering Contradiction:
Improvetelemetry processing capabilityVSAvoidenergy consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent extracts the energy-intensive data transmission and processing operations from the host processor and relocates them to a dedicated processor within the memory module. This extraction eliminates unnecessary data movement and processing operations, thereby reducing overall energy consumption while maintaining telemetry processing capability.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The dedicated processor within the memory module performs telemetry processing functions autonomously without requiring host processor involvement. This self-service capability allows the system to process telemetry data locally using available computational resources, eliminating the need for energy-consuming data transmission to the host processor.

Inventive Principle:
Principle #25Self-service

3Adaptability or versatility

If general-purpose processors are used for telemetry processing, then programming flexibility is provided, but unpredictable delays occur

Engineering Contradiction:
Improveprogramming flexibilityVSAvoidprocessing delay
Core Design Contradiction:
Adaptability or versatilityVSLoss of time

Solution Approach 1:

The patent segments the processing functions by dedicating a specific processor within the memory module to handle telemetry processing tasks. This segmentation isolates telemetry processing from general-purpose processing, eliminating unpredictable delays caused by host processor scheduling while maintaining programming flexibility through dedicated processing capabilities.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS20250298712A1Programmable processor for memory telemetry
Publication Date: 2025.09.25 MICRON TECHNOLOGY INC
  • US20250298712A1 patent drawing
  • US20250298712A1 patent drawing
  • US20250298712A1 patent drawing

AI summary

A memory sub-system includes a processor to store a reference value in a register, wherein the reference value represents a total available bandwidth of a memory sub-system. The processor is further configured to measure a current bandwidth usage within the memory sub-system, and determine a percentage of available bandwidth of the memory sub-system based on the current bandwidth usage and the reference value in the register. The processor is further configured to collect a set of data values representative of a latency statistic in the memory sub-system, and determine a moving average of the set of data values based on a predefined number of recent data values to smooth fluctuations in the latency statistic. The processor is further configured to store the moving average in a designated register in the memory sub-system.