DRAM Column Page Mode for Lower-Latency Matrix Access

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Solution Overview

Problem

Existing memory access methods in DRAM devices are inefficient for accessing data from a column of a matrix, requiring multiple row activations to retrieve a single column element, leading to increased power consumption and latency.

Innovation Solution

Implementing a column page mode that concurrently activates memory cells along one physical row of a set of memory array tiles, allowing simultaneous access to a column of data without iteratively activating single rows, and using a buffer to reorder data for efficient communication.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of information

If multiple row activations are used to access column data, then data access completeness is improved, but power consumption increases

Engineering Contradiction:

Improvedata access completenessVSAvoidpower consumption

Core Design Contradiction:

Loss of informationVSUse of energy by moving object

Solution Approach 1:

The memory array is divided into multiple independently controllable subarrays, allowing selective activation of only those subarrays containing the desired column data, rather than activating entire rows across all subarrays

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces a column page mode that accesses data along the column dimension by activating specific rows in selected subarrays simultaneously, rather than the traditional row-by-row activation approach

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Loss of information

If multiple row activations are used to access column data, then data access completeness is improved, but access time increases

Engineering Contradiction:

Improvedata access completenessVSAvoidaccess time

Core Design Contradiction:

Loss of informationVSLoss of time

Solution Approach 1:

Multiple subarray activations are merged into a single column page mode operation, allowing simultaneous access to column data across multiple subarrays in one go rather than sequential row-by-row access

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The column page mode pre-activates all necessary subarrays and data paths before the actual data read operation, ensuring that column data can be accessed immediately without iterative row activation delays

Inventive Principle:

Principle #10Preliminary action

3Measurement precision

If iterative row activation is used, then data access accuracy is improved, but data access efficiency deteriorates

Engineering Contradiction:

Improvedata access accuracyVSAvoiddata access efficiency

Core Design Contradiction:

Measurement precisionVSProductivity

Solution Approach 1:

The memory access system dynamically switches between traditional row page mode and column page mode based on access patterns, optimizing for both accuracy and efficiency in different operational contexts

Inventive Principle:

Principle #15Dynamics

Data Source

PatentUS20250307132A1Row and column page accesses

Publication Date: 2025.10.02 RAMBUS INC

AI summary

A memory device has a row access page mode that concurrently activates the memory cells along one physical row of an array of memory array tiles (MATs) and also has a column access page mode that concurrently activates the memory cells along one physical row of each of a set of MATs that are not in the same row or column as the other MATs in the set. The memory device may store data representing the elements of a matrix of values. Each physical row of the memory array may store values that correspond to a row of the matrix. The row access page mode may be used to access a set of data corresponding to a row (or portion of a row) of the matrix. The column access page mode may be used to access a set of data corresponding to a column of the matrix.