Out-of-Order Wordline Programming for Per-Unit P2L Mapping
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Solution Overview
Problem
Existing memory devices require a global P2L mapping data structure stored in volatile memory, leading to increased costs, complex media management, and power loss handling complications due to the need for frequent updates and retention of this data structure.
Innovation Solution
Implementing out-of-order programming of memory cells, where the first wordline is programmed after adjacent wordlines, allowing the P2L mapping data structure to be stored within each physical unit of memory, eliminating the need for a global volatile memory-based solution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a global P2L mapping data structure is stored in volatile memory, then the mapping can be quickly accessed and updated, but the hardware cost increases and power loss handling becomes complex
Solution Approach 1:
The patent divides the global P2L mapping data structure into per-physical-unit mapping structures stored within each physical unit's non-volatile memory. This segmentation eliminates the need for a centralized volatile memory structure, reducing hardware complexity while maintaining data integrity through non-volatile storage.
Solution Approach 2:
The patent creates local copies of the P2L mapping data structure within each physical unit's non-volatile memory. These local copies replicate the functionality of the global mapping structure without requiring access to volatile memory, enabling persistent storage and simplified media management.
2Device complexity
If the first wordline is programmed sequentially after adjacent wordlines, then the P2L mapping data structure can be stored within each physical unit, but the programming operation sequence changes
Solution Approach 1:
The patent implements dynamic programming sequences where the first wordline can be programmed at different positions relative to adjacent wordlines. This flexibility allows the system to optimize programming operations by storing P2L mapping data in non-volatile memory within each physical unit, reducing hardware complexity while maintaining programming efficiency through adaptive sequencing.
Data Source
AI summary
A memory device includes a memory array comprising memory cells associated with a plurality of wordlines control logic that is to perform operations including: causing memory cells of a physical unit of the memory array to be programmed starting at a second wordline, which is adjacent to a first wordline of the memory array, and proceeding sequentially through a plurality of sequentially-ordered wordlines of the physical unit, wherein the first wordline is associated with memory cells that are adjacent to one or more select gate (SG) transistors of the memory array, and the sequentially-ordered wordlines are numbered according to a distance away from the one or more SG transistors; and at least one of after the memory cells associated with the second wordline are programmed or after completion of programming the physical unit, causing the memory cells associated with the first wordline to be programmed.