Calibrated I/O Buffer Impedance for Drive and Split Termination
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Solution Overview
Problem
High-speed signal integrity issues arise in chip-to-chip interconnects due to transmission line effects like reflections, attenuation, and cross-talk, particularly in SDRAM memory systems, where existing solutions lack dynamic impedance control and often require external resistors, increasing costs and power consumption.
Innovation Solution
A combined drive and termination circuit with variable impedance pull-up and pull-down networks, dynamically configurable between drive and termination modes, using transistors in parallel to adjust impedance, and a calibration mechanism to set optimal transistor enablement for different operating conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If fixed external resistors are used for termination, then signal integrity is improved, but device complexity and cost increase
Solution Approach 1:
The patent combines the drive function and termination function into a single integrated circuit block. The termination resistors are integrated on-die rather than being external discrete components, eliminating the need for external resistors while maintaining signal integrity. This merging of functions directly resolves the contradiction by reducing device complexity and external component requirements while preserving the signal integrity benefits of proper termination.
Solution Approach 2:
The I/O buffer circuit is designed to perform multiple functions: driving signals during write operations and providing termination during read operations. The same circuit block dynamically switches between drive mode and termination mode, making it a universal component that eliminates the need for separate dedicated termination resistors. This multi-functionality directly addresses the contradiction by reducing external component count while maintaining proper signal termination.
2Reliability
If separate drive and termination circuits are used, then signal integrity is improved, but power consumption increases
Solution Approach 1:
The patent merges the drive circuit and termination circuit into a single integrated I/O buffer that dynamically switches between modes. During write operations, the circuit operates in drive mode with low output impedance. During read operations, the same circuit switches to termination mode with matched impedance. This single circuit performing both functions eliminates the need for separate always-on termination circuits, thereby reducing overall power consumption while maintaining signal integrity during read operations.
Solution Approach 2:
The I/O buffer dynamically switches between drive mode and termination mode based on the operational phase (write vs. read). This periodic switching allows the circuit to optimize its impedance characteristics for the current operation while minimizing power consumption by not maintaining termination resistance continuously. The dynamic mode switching resolves the contradiction by providing signal integrity only when needed (during reads) rather than continuously.
3Reliability
If dynamic impedance control is implemented, then signal integrity at high speeds is improved, but device complexity increases
Solution Approach 1:
The patent combines the drive transistors and termination resistors into a single integrated circuit block with unified control logic. The same control signals that manage the drive function also control the termination function, eliminating the need for separate control circuits. This merging approach enables dynamic impedance control for high-speed signals while minimizing the increase in device complexity through shared control infrastructure.
Solution Approach 2:
The I/O buffer is designed as a universal circuit that handles both drive and termination functions with a single control mechanism. The circuit dynamically reconfigures its impedance based on operational mode (write or read), providing high-speed signal integrity without requiring separate dedicated control circuits for each function. This multi-functionality achieves dynamic impedance control while limiting complexity growth through shared control logic.
Data Source
AI summary
A system and method of performing off chip drive (OCD) and on-die termination (ODT) are provided. A common pull-up network composed of transistors and a common pull-down network composed of transistors are employed to implement both of these functions. In drive mode, the pull-up network is configured to produce a calibrated drive impedance when an “on” output is to be generated, and the pull-up network is configured to produce a calibrated drive impedance when an “off” output is to be generated. In termination mode, the pull-up network and the pull-down network are configured to produce a calibrated pull-up resistance and pull-down resistance respectively such that together, they form a split termination.