Calibrated Sense Amplifier Circuit for Low-Margin Memory Readout
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Solution Overview
Problem
Existing sense amplifiers face insufficient sensing margins due to device mismatch and array noise, leading to data reading and writing errors, which are not adequately addressed by current offset-cancellation sense amplifiers.
Innovation Solution
A sense amplifier structure with two independently controllable inverters, where the input and output ends of the first inverter are connected through a calibration transistor, allowing for shorting and utilizing the inverter's switching point to amplify the sensed voltage, thereby increasing the sensing margin.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If offset-cancellation sense amplifiers are used to compensate for device mismatch, then sensing margin is improved, but other factors contributing to sensing margin losses are not adequately addressed
Solution Approach 1:
The patent segments the sensing margin improvement task into multiple independent error compensation mechanisms: device mismatch compensation through offset cancellation, array noise compensation through dedicated circuitry, and other error factor compensation. Each mechanism operates independently to address specific error sources, thereby achieving comprehensive coverage without relying on a single approach.
Solution Approach 2:
The patent employs parameter changes by dynamically adjusting compensation parameters based on detected error characteristics. The system monitors multiple error sources and modifies compensation parameters in real-time to optimize sensing margin under varying conditions, addressing the limitation of fixed offset-cancellation approaches.
2Manufacturing precision
If device mismatch is compensated for, then sensing margin loss is reduced, but the overall sensing margin remains insufficient due to other factors
Solution Approach 1:
The patent separates device mismatch compensation from other error compensations into distinct functional blocks. The device mismatch compensation handles transistor parameter variations, while separate array noise compensation and other error compensation circuits address their respective error sources, achieving comprehensive sensing margin improvement.
Solution Approach 2:
The patent merges multiple compensation mechanisms into a unified sense amplifier system. The output of device mismatch compensation, array noise compensation, and other error compensation are combined to produce the final sensed signal, thereby achieving cumulative sensing margin improvement that addresses all error factors.
Data Source
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AI summary
Embodiments of the present application relate to the field of memories and provide a sense amplifier. The sense amplifier includes: a first transistor electrically connected between a first power supply node and a complementary readout bit line, a control end of the first transistor being connected to a control end of a third transistor; a second transistor electrically connected between a second power supply node and a readout bit line, a control end of the second transistor being connected to a control end of a fourth transistor; the third transistor electrically connected between the complementary readout bit line and a third power supply node; the fourth transistor electrically connected between the readout bit line and a fourth power supply node; and a first calibration transistor connected between the complementary readout bit line and the control end of the third transistor. The first power supply node is connected to a first power supply voltage through a first switch element; the second power supply node is connected to the first power supply voltage through a second switch element; the third power supply node is connected to a second power supply voltage through the third switch element; the fourth power supply node is connected to the second power supply voltage through a fourth switch element.