CAM-Based Row Hammering Protection in DRAM
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Solution Overview
Problem
Semiconductor memory devices, particularly DRAMs, are susceptible to data corruption due to 'row hammering,' where repeated activation of one memory row can corrupt adjacent rows, leading to memory errors, which existing solutions cannot effectively address without excessive die area and gate count requirements.
Innovation Solution
Implementing a content addressable memory (CAM) to track the activation counts of memory rows, allowing for targeted refresh of adjacent rows before data corruption occurs, using a threshold-based system to determine when corrective action is necessary, thereby reducing the need for individual counters for each row.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If individual counters are implemented for each memory row to track activation counts, then row hammering protection is improved, but die area and gate count requirements increase excessively
Solution Approach 1:
The patent merges the activation counting function into the existing CAM structure used for address tracking. Instead of implementing separate counters for each row, the system utilizes the CAM's inherent address matching capability to track activations. When a row address is accessed, the CAM automatically detects if it's been accessed before within the refresh period, eliminating the need for additional counter circuits and reducing die area while maintaining row hammering protection.
Solution Approach 2:
The CAM structure is made multi-functional by using it for both address tracking and activation counting purposes. The same hardware structure that tracks which rows need refreshing is also used to count activations and detect row hammering attempts. This universal use of the CAM reduces overall hardware requirements and prevents the need for dedicated counter circuits for each row.
2Reliability
If individual counters are implemented for each memory row to track activation counts, then row hammering protection is improved, but device complexity increases
Solution Approach 1:
The patent combines multiple functions (address tracking, activation counting, and refresh management) into a single CAM-based system. By merging these functions, the patent eliminates the need for separate counter circuits, comparison logic, and control mechanisms that would otherwise be required for each row, thereby reducing gate count and device complexity while maintaining effective row hammering protection.
Solution Approach 2:
The CAM structure performs multiple functions simultaneously: it tracks row addresses, counts activations, determines refresh needs, and detects row hammering patterns. This multi-functionality reduces the overall device complexity by eliminating redundant circuits and simplifying the control logic compared to a system with individual counters for each row.
Data Source
AI summary
Activation of portions of a memory is tracked to allow an affected portion of the memory to be refreshed before it is corrupted by multiple activations. An address for the accessed portion of memory, called the aggressor row, is compared to addresses stored in a content addressable memory (CAM). If the address is not already stored in the CAM, it is stored, casting out another address if necessary, and a count based on an Others value is stored in the CAM with the address. If the address is already stored in the CAM, its associated count is incremented. If a count associated with an address exceeds a threshold based on a maximum activation count, another portion of memory, such as a victim row of memory adjacent to the aggressor row of memory, is refreshed, and the count reset.