Digital Storage TRIZ Cases

A FeSRAM cell uses segmented access and programming transistors to maintain non-volatile states without exposing low-voltage SRAM devices to high stress.

A hash-based filter identifies victim rows while the cache reduces electromagnetic crosstalk and defends against row hammering attacks.

Monotonic reference current sweeps resolve PVT-induced resistance shifts, ensuring accurate read operations across varying environmental conditions.

A semiconductor device performs self-write operations by internally generating read and write strobe signals to copy data within the core circuit.

Content addressable memory tracks activation counts to refresh adjacent rows, preventing row hammering errors without adding individual counters.

Refresh address control circuit generates multiple row hammer refresh sequences to protect memory cells from data degradation.

A nonvolatile semiconductor memory device uses segmented unit cell arrays and a control circuit to accumulate electric charge in parasitic capacitance at staggered times.

A drive control signal generation circuit adjusts active voltage levels supplied to word lines during refresh operations.

Supply switches disconnect voltage from charged inverters to eliminate charge contention and improve write margin in ultra-low power applications.

Redistribution layer merges memory channels and I/O signal paths to consolidate active connections.

Segmented memory blocks reduce wiring capacitance to overcome signal propagation delays in high-density content addressable memories.

A semiconductor memory apparatus uses a common current unit to drive sensing and programming currents from a single voltage source.

A resistive memory read circuit maintains constant bit line voltage via a dedicated controller to linearize sensing current for accurate multi-level data detection.

Synchronizing the disable signal with the command clock eliminates execution uncertainty windows that cause data corruption.

A switching element uses capacitive coupling to generate a third voltage for detecting memory states in resistivity changing cells.

Insulator spaces surrounding stacked body resist thermal conduction from magnetoresistance element, preventing heat damage to control circuits.

A magnetic memory operating method initializes free layers using sequential current and field pulses to establish stable anti-parallel magnetization states.

Universal detection circuits merge signal identification with response priority, reducing die area requirements for stacked memory packages.

An access signal generator adjusts voltage magnitudes to compensate for line resistance in scaled cross-point memory arrays.

A shared level shifter reduces area and power consumption by serving multiple word-line drivers.

Controlled charge delivery prevents oscillation between resistance states in reversible switching materials during programming operations.

A voltage regulating device adjusts memory array operating voltage based on measured temperature and fabrication data.

Segmented word lines with local current limiters prevent voltage crashes during parallel writes, maintaining stable operation.

Periodic wordline underdrive pulses maintain static noise margin and write margins, preventing data flipping during low supply voltage operations.

A read circuit with variable current sources adjusts reference and read currents to compare input voltages across memory sectors.

A noise generating block creates artificial electrical noise within semiconductor memory peripheral circuits during wafer testing.

A burst mode address comparator reduces SRAM power consumption by skipping unnecessary sense amplifier pre-charging during consecutive row accesses.

A data verification device writes high frequency sequence data to memory and compares voltage values to determine DFE strength.

Differentiating wiring structures prevents void formation in reference resistors, improving magnetic memory device reliability.

A programmable lookup table configures a generic data scrambler to execute multiple algorithms, resolving the complexity of testing diverse 3D memory stacks.

A level shifter raises gate voltage above source potential to stop PMOS leakage in dual rail SRAM.

A semiconductor memory device uses dummy cells to mimic static cell characteristics for precise timing control.

Adjusting electrical pulse fall time improves phase change memory cell programming accuracy.

Different stacking orders in magnetic memory cells enable binary data storage via resistance comparison, addressing speed and non-volility trade-offs.

A multi-bit magnetic random access memory cell uses a tilted magnetic anisotropy axis to switch magnetization direction for storing multiple logic states.

Segmented pre-driver and main driver transistors lower leakage current and minimize physical size of column select circuitry.

A resistive memory controller uses look-ahead bits to detect data errors and trigger targeted refresh operations.

Switchable paths interconnect subsets of variable resistive elements to average process variations and improve dictionary weight precision.

Two-step IMS encoding generates search and threshold voltages to protect storage data integrity.

A parallel data storage system segments sectors into cells distributed across multiple devices via a switch.

A static NAND ternary content addressable memory cell uses parallel pull-down and series pull-up transistors to eliminate pre-charging requirements.

Merging sense amplifiers with compensation circuitry reduces area while correcting threshold voltage mismatches for reliable operation.

A semiconductor integrated circuit core voltage generator maintains stable internal potential using a dedicated feedback loop.

A semiconductor memory device generates internal low-frequency clock signals from high-frequency external inputs for testing.

A memory device stores parameter codes in a mode register to configure default and optional data receiver offset calibration settings.

A semiconductor memory device rearranges memory blocks within banks to different addressable orders for optimized word line activation.

Multiplexers merge test arrays with memory cells to improve measurement precision without increasing area overhead.

Command timing circuit segments signal paths to match specific clock frequency ranges, resolving timing inaccuracies across wide operational bands.

Preset lines generate magnetic fields to orient magnetic elements in spin transfer torque memory cells.