Parity Error Synchronization in Memory Devices
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Solution Overview
Problem
Existing memory devices face challenges in synchronizing parity error command blocking, leading to uncertainty in command execution due to delayed parity error detection and masking, which can result in data corruption and inefficiencies.
Innovation Solution
Implementing a system that activates a parity error command path disable signal after the command clock for the command prior to the parity error, ensuring that only the command with the parity error and subsequent commands are disabled, while allowing prior external commands to execute, by using a programmed parity latency value to synchronize parity error detection and masking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If parity error detection and masking is implemented immediately upon detection, then data corruption is prevented, but command execution uncertainty increases due to delayed detection and masking
Solution Approach 1:
The system performs preliminary synchronization by aligning the parity error disable signal with the command clock timing. The parity error disable signal is generated to coincide with the command clock edge, ensuring that commands are disabled at the precise moment they are latched, eliminating the uncertainty window while maintaining data integrity.
Solution Approach 2:
The system uses feedback from the parity error detection mechanism to generate a disable signal that is timed relative to the command clock. The feedback loop synchronizes the disable signal generation with the command latching timing, ensuring that the disable signal arrives at the correct moment to prevent corruption without creating execution uncertainty.
2Reliability
If parity error disable signal is activated immediately upon error detection, then data corruption is minimized, but prior external commands may be incorrectly blocked
Solution Approach 1:
The system determines in advance which commands should be disabled by synchronizing the parity error disable signal with the command clock timing. By aligning the signal generation with the command latching edge, the system precisely identifies only the commands that need to be blocked, avoiding incorrect blocking of prior external commands while maintaining data integrity.
3Measurement precision
If command blocking is synchronized with command clock timing, then command execution precision is improved, but system complexity increases due to timing synchronization requirements
Solution Approach 1:
The system merges the parity error disable signal generation with the existing command clock timing infrastructure. By using the command clock edge as the reference point for signal generation, the system achieves precise timing synchronization without requiring separate complex timing circuits, thus improving command timing precision while minimizing additional system complexity.
Data Source
AI summary
Systems and methods providing for a parity error synchronization based on a programmed parity latency value by delaying an activation of a command disable signal to disable internal commands such that the command disable signal activates just prior to the parity error command.