Resistive Memory Error Correction with Look-Ahead Bits
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Solution Overview
Problem
Emerging nonvolatile memories, such as resistive memories, face data retention and corruption issues due to high temperatures and electromagnetic interference, leading to system crashes, data corruption, and security vulnerabilities, with existing solutions like flash memory suffering from low write endurance and scaling issues.
Innovation Solution
A resistive nonvolatile memory system that includes look-ahead bits and error correction code (ECC) bits, where the memory controller performs read operations to detect errors and initiates strong or weak refreshes based on error thresholds, ensuring data integrity and retention by correcting and rewriting data bits and look-ahead bits accordingly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If resistive nonvolatile memories are used to improve write endurance and speed, then productivity is improved, but data retention and reliability deteriorate under high temperatures
Solution Approach 1:
The patent applies preliminary action by performing refresh operations on memory data before errors occur. The system periodically reads data from resistive memory cells and rewrites it to correct potential errors caused by high temperature, preventing data corruption before it happens during normal operation.
Solution Approach 2:
The patent implements feedback by reading data from memory cells, analyzing it for errors using ECC codes, and using this information to determine whether refresh operations are needed. The system continuously monitors data quality and adjusts refresh frequency based on detected error rates and temperature conditions.
2Reliability
If refresh operations are performed frequently to improve data retention, then reliability is improved, but productivity deteriorates due to increased write operations
Solution Approach 1:
The patent applies partial action by performing refresh operations selectively rather than continuously. The system refreshes only those memory blocks that show signs of degradation or error, determined through ECC analysis and temperature monitoring, thereby reducing unnecessary write operations while maintaining data integrity.
Solution Approach 2:
The patent changes the parameter of refresh frequency dynamically based on operating conditions. The system adjusts how often refresh operations occur based on detected error rates, temperature levels, and memory block history, optimizing the balance between reliability and productivity.
3Reliability
If error detection and correction mechanisms are implemented to improve reliability, then data integrity is improved, but device complexity increases
Solution Approach 1:
The patent introduces an intermediary error correction code layer between the memory storage and data processing functions. ECC codes are calculated from data blocks and stored separately, then used to detect and correct errors without requiring complex real-time analysis of the actual data content, simplifying the overall error handling mechanism.
4Reliability
If look-ahead bits are used to predict data quality to improve reliability, then data integrity is improved, but the number of stored bits increases
Solution Approach 1:
The patent uses look-ahead bits as disposable quality indicators that are periodically updated and discarded. These bits provide temporary information about data quality trends and are refreshed along with the data blocks they monitor, allowing error prediction without requiring permanent additional storage capacity.
Data Source
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AI summary
A memory system includes a resistive nonvolatile memory array configured to store data and error correction code (ECC) bits and a memory controller. The memory controller is configured to detect a number of errors among the stored look-ahead bits, compare the number of look-ahead bit errors to a threshold number of bit errors, perform a strong refresh of the data and look-ahead bits stored in the resistive nonvolatile memory array when the number of look-ahead bit errors equals or exceeds the threshold, and perform a weak refresh of the data and look-ahead bits by refreshing only units of stored data having data bit errors and look-ahead bits having look-ahead bit errors when the number of look-ahead bit errors is less than the threshold.