Memory Test Circuit Multiplexer Integration
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Solution Overview
Problem
Ensuring the reliability of memory devices requires effective characterization of memory cells, which existing technologies struggle to achieve efficiently, especially in terms of area overhead and functional integration.
Innovation Solution
Incorporating a test array with write and read multiplexers within the memory array, allowing test cells to function as both data storage and characterization measurement units, reducing the need for additional area and enabling simultaneous data storage and cell characterization through controlled signal operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If separate test circuits are added for memory cell characterization, then measurement capability is improved, but area overhead increases
Solution Approach 1:
The patent combines the test circuit functionality with the existing memory array structure by using multiplexers to share data lines between normal memory operations and test operations. This merging approach allows cell characterization to be performed without adding separate dedicated test circuits, thereby improving measurement capability while avoiding significant area overhead.
Solution Approach 2:
The multiplexers in the test circuit enable data lines to serve dual purposes: normal memory data transmission and test signal routing for cell characterization. This multi-functionality allows the same hardware infrastructure to support both operational and testing functions, eliminating the need for additional dedicated test circuitry and reducing area overhead.
2Measurement precision
If dedicated test circuits are implemented, then cell characterization accuracy is improved, but device complexity increases
Solution Approach 1:
The test circuit is merged with the existing memory array architecture, using the same data lines and multiplexers already present in the memory structure. This integration approach achieves accurate cell characterization without introducing separate complex test circuitry, thereby improving measurement precision while maintaining relatively simple device complexity.
Solution Approach 2:
The multiplexers serve multiple functions by routing signals for both normal memory operations and test operations through the same data lines. This multi-functionality reduces the need for additional dedicated test circuits, achieving accurate cell characterization while avoiding significant increases in device complexity.
3Area of stationary object
If memory array is used for both data storage and testing, then area efficiency is improved, but functional interference may occur
Solution Approach 1:
The multiplexers are configured to switch between normal memory operations and test operations based on control signals. This preliminary switching action ensures that test signals are routed only when needed, preventing interference with normal memory data transmission and storage operations while maintaining area efficiency through shared infrastructure.
Solution Approach 2:
The test circuit uses dynamic multiplexing to switch data line functionality between normal memory operations and test operations. This dynamic switching capability allows the same physical infrastructure to serve different functions at different times, improving area efficiency while preventing functional interference through time-division multiplexing controlled by measurement signals.
Data Source
AI summary
A memory test circuit is provided. The memory test circuit is disposed in a memory array and including: a test array, including test cells out of memory cells of the memory array; a write multiplexer, configured to selectively output one of a test signal and a reference voltage based on a write measurement signal, wherein the test signal is output to write into at least one test cell and the reference voltage is output to a sense amplifier; and a read multiplexer, configured to selectively receive and output one of a readout signal corresponding to the test signal and an amplified signal based on a read measurement signal, wherein the readout signal is read from the at least one test cell and the amplified signal is obtained for a read margin evaluation from the sense amplifier by amplifying a voltage difference between the readout signal and the reference voltage.