Semiconductor Memory Block Select Decoding Circuit
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Solution Overview
Problem
Conventional semiconductor memory devices with multiple memory banks experience increased power consumption and circuit noise due to the concurrent activation of edge memory blocks, which requires a higher word line enable voltage and results in inefficient word line activation ratios.
Innovation Solution
The semiconductor memory device rearranges memory blocks within each bank to have different addressable orders, allowing only two edge memory blocks to be activated in one bank while activating normal memory blocks in the others, reducing the number of concurrently activated word lines and thus lowering the word line enable voltage and noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If edge memory blocks are concurrently activated in multiple memory banks, then memory access capability is improved, but power consumption increases and circuit noise increases
Solution Approach 1:
The patent divides memory banks into different groups (first group and second group) and segments the activation of edge memory blocks across these groups. By controlling decoders in different groups independently, the system can activate edge memory blocks in a staggered manner rather than simultaneously, reducing peak power consumption while maintaining overall memory access capability.
Solution Approach 2:
The patent implements periodic activation of edge memory blocks across different memory bank groups. The first decoder activates edge memory blocks in the first group during a first time period, while the second decoder activates edge memory blocks in the second group during a second time period. This periodic, time-separated activation reduces simultaneous word line activation and associated power consumption.
2Productivity
If edge memory blocks are concurrently activated in multiple memory banks, then memory access capability is improved, but circuit noise increases
Solution Approach 1:
The patent segments memory banks into different groups with independent decoders, allowing edge memory block activation to be distributed across groups rather than concentrated simultaneously. This segmentation reduces the number of concurrently activated word lines, thereby reducing circuit noise while preserving memory access capability through coordinated activation across groups.
Solution Approach 2:
The patent employs periodic activation where edge memory blocks in different memory bank groups are activated at different time periods. The first decoder operates during a first time period and the second decoder operates during a second time period, creating a time-separated activation pattern that reduces simultaneous switching noise and improves signal integrity.
3Speed
If more word lines are activated concurrently, then memory access speed is improved, but word line enable voltage requirement increases
Solution Approach 1:
The patent segments the activation of word lines by dividing memory banks into groups with independent decoders. Each decoder activates word lines in its associated memory bank group independently, allowing the system to maintain high memory access speed through parallel group activation while reducing the peak voltage requirement by avoiding simultaneous activation of all word lines across all banks.
Solution Approach 2:
The patent implements periodic word line activation where different groups of word lines are activated in different time periods. The first decoder activates word lines in the first group during a first time period, while the second decoder activates word lines in the second group during a second time period. This time-separated activation maintains memory access speed through efficient parallel processing while reducing the peak enable voltage requirement.
Data Source
AI summary
Semiconductor memory devices, block select decoding circuits and a method of activating a word line are provided. An example semiconductor memory device may include a plurality of memory banks. Each of the plurality of memory banks may include memory blocks which may be arranged in different addressable orders. If two edge memory blocks are activated in a given one of the plurality of memory banks, a non-edge memory block may be concurrently activated in at least one of remaining memory banks other than the given one memory bank. Accordingly, a number of concurrently activated memory blocks, a voltage required to enable a word line and noise may be reduced. The example semiconductor device may include the example block select decoding circuit, and likewise may perform the example method of activating a word line with an activation of a reduced number of memory blocks.