Generic Data Scrambler for 3D Memory BIST Testing
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Solution Overview
Problem
The complexity of data scrambling in 3D stacked memory devices, which varies by manufacturer, poses a challenge in effective testing, as conventional methods are hard-coded and impractical for multiple algorithms, leading to inefficiencies in defect detection and manufacturing yield.
Innovation Solution
A generic data scrambler with a programmable lookup table is introduced, capable of implementing multiple scrambling algorithms, allowing for efficient data scrambling and descrambling, and is process-independent, requiring no hardware changes, thus supporting built-in self-test operations across different memory types.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional hard-coded data scrambling methods are used, then the testing process is simple to implement, but the adaptability to different memory device designs is poor
Solution Approach 1:
The data scrambler is designed as a universal component that can perform multiple scrambling algorithms (e.g., first algorithm and second algorithm) through programmable control. The control circuit receives algorithm selection signals and configures the scrambler accordingly, allowing a single device to handle different memory device designs without requiring separate hard-coded implementations for each algorithm.
Solution Approach 2:
The data scrambler transitions from a static hard-coded implementation to a dynamic, reconfigurable system. The control circuit dynamically adjusts the scrambler's operation based on the selected algorithm, enabling the same hardware to adapt its behavior to match different memory device requirements through runtime configuration rather than fixed design.
2Adaptability or versatility
If multiple scrambling algorithms are implemented with separate hard-coded circuits, then the adaptability to different memory devices is improved, but the device complexity and manufacturing cost increase
Solution Approach 1:
Instead of manufacturing different hardware circuits for each scrambling algorithm, the invention uses a universal scrambler that can be programmed to implement multiple algorithms. This single manufacturable design supports various memory device types through software/firmware configuration, eliminating the need for complex multi-variant manufacturing processes.
Solution Approach 2:
The invention replaces physical hardware copies (separate circuits for each algorithm) with a single reconfigurable hardware instance that can be logically copied or instantiated in different algorithmic states. The control circuit loads appropriate scrambling parameters and configurations to emulate different algorithm behaviors without requiring duplicate physical circuits.
3Measurement precision
If algorithm-specific test engines are used, then the testing precision for each memory type is optimized, but the overall system complexity and testing time increase
Solution Approach 1:
The test engine incorporates a universal data scrambler that can be configured for different algorithms, allowing a single test engine to maintain high testing precision across various memory device types. The control circuit selects and configures the appropriate scrambling algorithm based on the target memory device, ensuring optimal test coverage without requiring multiple specialized test engines.
Solution Approach 2:
The invention merges multiple algorithm-specific test capabilities into a single integrated test engine. By combining the data scrambler, control circuit, and test logic into one unified system that can dynamically configure its behavior, the invention reduces the number of separate testing operations needed while maintaining comprehensive defect detection coverage.
Data Source
AI summary
A generic data scrambler is provided for a built-in self-test (BIST) engine of a stacked memory device. The stacked memory device includes a memory stack of one or more memory layers; and a system element that is coupled with the memory stack. The system element includes a memory controller for the memory stack; a BIST circuit for testing of the memory stack; and a generic data scrambler for scrambling of data according to a data scrambling algorithm for the memory stack. The generic data scrambler includes a programmable lookup table to hold data factors for each possible outcome of the data scrambling algorithm, and the programmable lookup table is to generate a set of data factors based on addresses of data for testing of the memory stack.